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data sheet v1.5 2011-03 microcontrollers 8-bit xc87xclm 8-bit single-chip microcontroller www..net
edition 2011-03 published by infineon technologies ag 81726 munich, germany ? 2011 infineon technologies ag all rights reserved. legal disclaimer the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infineon technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warr anties of non-infringement of intellectual property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies components may be used in life-support devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
data sheet v1.5 2011-03 microcontrollers 8-bit xc87xclm 8-bit single-chip microcontroller
xc87xclm data sheet v1.5, 2011-03 xc87x data sheet revision history: v1.5 2011-03 previous versions: v1.4 page subjects (major changes since last revision) changes from v1.4 201 0-08 to v1.5 2011-03 page 3 a new variant, saf-xc874cm-13f va 5v, has been ad ded in table 2. we listen to your comments any information within this docu ment that you feel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com
xc87xclm table of contents data sheet i-1 v1.5, 2011-03 1 summary of features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 general device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1 processor architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2.1 memory protection strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.2.1.1 flash memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.2.2 special function regist er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.2.2.1 address extension by mappi ng . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.2.2.2 address extension by paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.2.3 bit protection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.2.3.1 password register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.2.4 xc87x register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.2.4.1 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.2.4.2 mdu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.2.4.3 cordic registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.2.4.4 system control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.2.4.5 wdt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.2.4.6 port registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.2.4.7 adc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.2.4.8 timer 2 compare/capture unit registers . . . . . . . . . . . . . . . . . . . . . 47 3.2.4.9 timer 21 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.2.4.10 ccu6 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.2.4.11 uart1 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.2.4.12 ssc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.2.4.13 multican registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.2.4.14 ocds registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.2.4.15 flash registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.3 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.3.1 flash bank pagination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.4 interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.4.1 interrupt source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.4.2 interrupt source and vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.4.3 interrupt priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 3.5 parallel ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 3.6 power supply system with embedded voltage regulator . . . . . . . . . . . . 72 table of contents
xc87xclm table of contents data sheet i-2 v1.5, 2011-03 3.7 reset control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.7.1 module reset behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.7.2 booting scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.8 clock generation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 3.8.1 recommended external oscilla tor circuits . . . . . . . . . . . . . . . . . . . . . . 77 3.8.2 clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 3.9 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 3.10 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 3.11 multiplication/div ision unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 3.12 cordic coprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 3.13 uart and uart1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 3.13.1 baud-rate generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 3.13.2 baud rate generation using timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 91 3.14 normal divider mode (8-bit auto-reload timer) . . . . . . . . . . . . . . . . . . . . . 91 3.15 lin protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 3.15.1 lin header transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 3.16 high-speed synchronous serial interface . . . . . . . . . . . . . . . . . . . . . . . . . 94 3.17 timer 0 and timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 3.18 timer 2 and timer 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 3.19 timer 2 capture/compare unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 3.20 capture/compare unit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 3.21 controller area netw ork (multican) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 3.22 analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 3.22.1 adc clocking scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 3.22.2 adc conversion seq uence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 3.23 on-chip debug support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 3.23.1 jtag id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 3.24 chip identification number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 4 electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 4.1 general parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 4.1.1 parameter interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 4.1.2 absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 4.1.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 4.2 dc parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 4.2.1 input/output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 4.2.2 supply threshold characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 4.2.3 adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 4.2.3.1 adc conversion timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 4.2.4 power supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 4.3 ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 4.3.1 testing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 4.3.2 output rise/fall ti mes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
xc87xclm table of contents data sheet i-3 v1.5, 2011-03 4.3.3 power-on reset and pll timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 4.3.4 on-chip oscillator characte ristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 4.3.5 external data memory charac teristics . . . . . . . . . . . . . . . . . . . . . . . . 126 4.3.6 external clock drive xtal1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 4.3.7 jtag timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 4.3.8 ssc master mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 5 package and quality declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 5.1 package parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 5.2 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 5.3 quality declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
data sheet 1 v1.5, 2011-03 xc87xclm 8-bit single-chip microcontroller 1 summary of features the xc87x has the following features: ? high-performance xc800 core ? compatible with sta ndard 8051 processor ? two clocks per machine cycle architecture (for memory access without wait state) ? two data pointers ? on-chip memory ? 8 kbytes of boot rom ? 256 bytes of ram ? 3 kbytes of xram ? 64/52 kbytes of flash; (includes memory protection strategy) ? i/o port supply at 3.3 v or 5.0 v and core logic supply at 2.5 v (generated by embedded voltage regulator) (more features on next page) figure 1 xc87x functional units port 0 port 1 port 3 xc800 core uart adc 10-bit 8-channel boot rom 8k x 8 xram 3k x 8 ram 256 x 8 on-chip debug support timer 0 16-bit timer 1 16-bit timer 2 capture/ compare unit 16-bit uart1 ssc capture/compare unit 16-bit compare unit 16-bit 8-bit digital i/o 8-bit digital i/o 8-bit digital i/o port 4 port 5 mdu cordic multican timer 21 16-bit watchdog timer 8-bit digital i/o . 8-bit digital i/o flash 52k/64k x 8 8-bit analog input
xc87xclm summary of features data sheet 2 v1.5, 2011-03 features: (continued) ? power-on reset generation ? brownout detection fo r core logic supply ? on-chip osc and pll for clock generation ? loss-of-clock detection ? power saving modes ? slow-down mode ? idle mode ? power-down mode with wake-up ca pability via rxd or exint0 1) ? clock gating contro l to each peripheral ? programmable 16-bit watchdog timer (wdt) ? five ports ? up to 40 pins as digital i/o ? 8 dedicated analog inputs used as a/d converter input ? 8-channel, 10-bit adc ? four 16-bit timers ? timer 0 and time r 1 (t0 and t1) ? timer 2 and time r 21 (t2 and t21) ? multiplication/division unit fo r arithmetic operations (mdu) ? cordic coprocessor for computation of trigonometric, hy perbolic and linear functions ? multican with 2 nodes , 32 message objects ? two capture/compare units ? capture/compare unit 6 for pwm signal generation (ccu6) ? timer 2 capture/compare unit for va ious digital signal generation (t2ccu) ? two full-duplex serial in terfaces (uart and uart1) ? synchronous serial channel (ssc) ? on-chip debug support ? 1 kbyte of monitor rom (par t of the 8-kbyte boot rom) ? 64 bytes of monitor ram ? packages: ?pg-lqfp-64 ?pg-vqfn-48 ? temperature range t a : ? saf (-40 to 85 c) ? sax (-40 to 105 c) ? sak (-40 to 125 c) 1) sak product variant does not support power-down mode.
xc87xclm summary of features data sheet 3 v1.5, 2011-03 xc87x variant devices the xc87x product family features device s with different configurations, program memory sizes, package options, power supply voltage, temperatur e and quality profiles (automotive or industrial), to offer cost-e ffective solutions for different application requirements. the list of xc87x device configurations are summarized in table 1 . 2 types of packages are available : ? pg-lqfp-64, which is denoted by xc878 and; ? pg-vqfn-48, which is denoted by xc874 from these 5 different combinat ions of configuration, each are further made available in many sales types, which are grouped accord ing to device type, program memory sizes, power supply voltage, temper ature and quality pr ofiles (automotive or industrial), as shown in table 2 . table 1 device configuration device name can module lin bsl support mdu module xc87x nonono xc87xm no no yes XC87XCM yes no yes xc87xlm no yes yes xc87xclm yes yes yes table 2 device profile sales type device type program memory (kbytes) power supply (v) temp- erature (c) quality profile saf-xc878-13ffi 5v flash 52 5.0 -40 to 85 industrial saf-xc878m-13ffi 5v flash 52 5.0 -40 to 85 industrial saf-xc878cm-13ffi 5v flash 52 5.0 -40 to 85 industrial saf-xc878-16ffi 5v flash 64 5.0 -40 to 85 industrial saf-xc878m-16ffi 5v flash 64 5.0 -40 to 85 industrial saf-xc878cm-16ffi 5v flash 64 5.0 -40 to 85 industrial saf-xc878-13ffi 3v3 flash 52 3.3 -40 to 85 industrial saf-xc878m-13ffi 3v3 flash 52 3.3 -40 to 85 industrial
xc87xclm summary of features data sheet 4 v1.5, 2011-03 saf-xc878cm-13ffi 3v3 flash 52 3.3 -40 to 85 industrial saf-xc878-16ffi 3v3 flash 64 3.3 -40 to 85 industrial saf-xc878m-16ffi 3v3 flash 64 3.3 -40 to 85 industrial saf-xc878cm-16ffi 3v3 flash 64 3.3 -40 to 85 industrial saf-xc878-13ffa 5v flash 52 5.0 -40 to 85 automotive saf-xc878cm-13ffa 5v flash 52 5.0 -40 to 85 automotive saf-xc878lm-13ffa 5v flash 52 5.0 -40 to 85 automotive saf-xc878clm-13ffa 5v flash 52 5.0 -40 to 85 automotive saf-xc878-16ffa 5v flash 64 5.0 -40 to 85 automotive saf-xc878cm-16ffa 5v flash 64 5.0 -40 to 85 automotive saf-xc878lm-16ffa 5v flash 64 5.0 -40 to 85 automotive saf-xc878clm-16ffa 5v flash 64 5.0 -40 to 85 automotive sax-xc878-13ffa 5v flash 52 5 .0 -40 to 105 automotive sax-xc878cm-13ffa 5v flash 5 2 5.0 -40 to 105 automotive sax-xc878lm-13ffa 5v flash 5 2 5.0 -40 to 105 automotive sax-xc878clm-13ffa 5v flash 5 2 5.0 -40 to 105 automotive sax-xc878-16ffa 5v flash 64 5 .0 -40 to 105 automotive sax-xc878cm-16ffa 5v flash 6 4 5.0 -40 to 105 automotive sax-xc878lm-16ffa 5v flash 6 4 5.0 -40 to 105 automotive sax-xc878clm-16ffa 5v flash 6 4 5.0 -40 to 105 automotive sak-xc878-13ffa 5v flash 52 5 .0 -40 to 125 automotive sak-xc878cm-13ffa 5v flash 5 2 5.0 -40 to 125 automotive sak-xc878lm-13ffa 5v flash 5 2 5.0 -40 to 125 automotive sak-xc878clm-13ffa 5v flash 5 2 5.0 -40 to 125 automotive sak-xc878-16ffa 5v flash 64 5 .0 -40 to 125 automotive sak-xc878cm-16ffa 5v flash 6 4 5.0 -40 to 125 automotive sak-xc878lm-16ffa 5v flash 6 4 5.0 -40 to 125 automotive sak-xc878clm-16ffa 5v flash 6 4 5.0 -40 to 125 automotive saf-xc874lm-16fva 5v flash 64 5.0 -40 to 85 automotive table 2 device profile (cont?d) sales type device type program memory (kbytes) power supply (v) temp- erature (c) quality profile
xc87xclm summary of features data sheet 5 v1.5, 2011-03 as this document refers to all the derivatives, some de scription may not apply to a specific product. for simplicit y, all versions are referred to by the term xc87x throughout this document. ordering information the ordering code for infineo n technologies microcontrol lers provides an exact reference to the required produc t. this ordering code identifies: ? the derivative itself, i.e. its function set, the temper ature range, and the supply voltage ? the package and the type of delivery for the available ordering codes for the xc87 x, please refer to yo ur responsible sales representative or yo ur local distributor. saf-xc874cm-16fva 5v flash 64 5.0 -40 to 85 automotive saf-xc874cm-13fva 5v flash 52 5.0 -40 to 85 automotive sak-xc874lm-16fva 5v flash 64 5 .0 -40 to 125 automotive sak-xc874cm-16fva 5v flash 6 4 5.0 -40 to 125 automotive sak-xc874-16fva 5v flash 64 5 .0 -40 to 125 automotive sak-xc874lm-13fva 5v flash 5 2 5.0 -40 to 125 automotive sak-xc874cm-13fva 5v flash 5 2 5.0 -40 to 125 automotive sak-xc874-13fva 5v flash 52 5 .0 -40 to 125 automotive table 2 device profile (cont?d) sales type device type program memory (kbytes) power supply (v) temp- erature (c) quality profile
xc87xclm general device information data sheet 6 v1.5, 2011-03 2 general device information chapter 2 contains the block diagram, pin configur ations, definitions and functions of the xc87x. 2.1 block diagram the block diagram of the xc87x is shown in figure 2 . figure 2 xc87x block diagram adc port 0 port 1 port 3 uart 1 cordic ssc mdu timer 2 capture/ compare unit 8-kbyte boot rom 1) 256-byte ram + 64-byte monitor ram 3-kbyte xram 52/64-kbyte flash xc800 core t0 & t1 uart 1) includes 1-kbyte monitor rom p0.0 - p0.7 p1.0 - p1.7 p3.0 - p3.7 an0 ? an7 v aref v agnd clock generator 4 mhz on-chip osc pll xtal 1 xtal 2 internal bus v ddp v ssp v ddc v ssc reset tms mbc xc87x timer 21 ccu 6 multican port 4 port 5 p4.0 - p4.7 p5.0 - p5.7 wdt ocds tm
xc87xclm general device information data sheet 7 v1.5, 2011-03 2.2 logic symbol the logic symbols of the xc8 78 and xc874 are shown in figure 3 . figure 3 xc878 and xc874 logic symbol xc878 v ddp v ssp v ddc v ssc v aref v agnd xtal1 xtal2 tms mbc port 0 8-bit port 1 8-bit port 3 8-bit an0 ? an7 port 4 8-bit port 5 8-bit reset tm xc874 v ddp v ssp v ddc v ssc v aref v agnd xtal1 xtal2 tms mbc port 0 8-bit port 1 8-bit port 3 7-bit an1,an2, an4 ? an7 port 4 4-bit reset tm
xc87xclm general device information data sheet 8 v1.5, 2011-03 2.3 pin configuration the pin configuration of the xc878, which is based on the pg-lqfp-64, is shown in figure 4 , while that of the xc874, which is based on the pg-vqfn-48 package, is shown in figure 5 . figure 4 xc878 pin configurat ion, pg-lqfp-64 package (top view) v ddp xc878 123 45678910111213141516 17 18 19 28 27 26 25 24 23 22 21 20 32 31 30 29 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 53 54 55 56 57 58 59 60 61 49 50 51 52 reset p3. 5 p3. 4 an2 v ddp p1.3 p1.4 p5 . 0 p4. 2 p4. 1 p4. 0 p1.2 v ssp p5 . 1 an0 p0. 3 p0. 4 p0 . 5 p1 . 6 p1 . 7 v ssc v ddc xta l2 xta l1 tms mbc p1.0 p1.1 p1.5 an4 an3 an7 an5 an6 p3.0 p3.1 p3. 2 p3. 3 p3.6 p3.7 v aref v agnd p0 . 6 p0. 7 p4.5 p4.4 p4.6 p4.7 p5 . 5 p5.6 p5.7 p5 . 4 v ddp p0.0 n.c. tm p5 . 3 p4.3 p5 . 2 v ssp p0.2 p 0 . 1 an1
xc87xclm general device information data sheet 9 v1.5, 2011-03 figure 5 xc874 pin configurat ion, pg-vqfn-48 package (top view) xc874 123 456789101112 13 14 15 24 23 22 21 20 19 18 17 16 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 37 38 39 40 41 42 43 44 45 reset p3.5 p3 .4 p4 .2 p4.1 p0 .3 p0. 4 mbc p3 .2 p3 .3 p0.7 v ddp v ssp p0 .0 p0. 5 p1 .6 p1 .7 v ssc v ddc xt al2 xt al1 tms an2 v ddp v ssp an4 an5 an6 v aref v agnd p0. 2 p 0 . 1 p1.3 p1.4 p1.2 p1.0 p1.1 p1.5 p3.0 p3.1 p3.6 p4.3 p0 .6 p4.0 nc tm an7 an1
xc87xclm general device information data sheet 10 v1.5, 2011-03 2.4 pin definitions and functions the functions and default st ates of the xc87x extern al pins are provided in table 3 . table 3 pin definiti ons and functions symbol pin number (lqfp-64 / vqfn-48) type reset state function p0 i/o port 0 port 0 is an 8-bit bidi rectional general purpose i/o port. it can be used as alternate functions for the jtag, ccu6, uart, uart1, t2ccu, timer 21, multican, ss c and external bus interface. note: external bus interface is not available in xc874. p0.0 17/12 hi-z tck_0 t12hr_1 cc61_1 clkout_0 rxdo_1 jtag clock input ccu6 timer 12 hardware run input input/output of capture/compare channel 1 clock output uart transmit data output p0.1 21/14 hi-z tdi_0 t13hr_1 rxd_1 rxdc1_0 cout61_1 exf2_1 jtag serial data input ccu6 timer 13 hardware run input uart receive data input multican node 1 receiver input output of ca pture/compare channel 1 timer 2 external flag output p0.2 18/13 pu ctrap_2 tdo_0 txd_1 txdc1_0 ccu6 trap input jtag serial data output uart transmit data output/clock output multican node 1 transmitter output
xc87xclm general device information data sheet 11 v1.5, 2011-03 p0.3 63/1 hi-z sck_1 cout63_1 rxdo1_0 a17 ssc clock input/output output of ca pture/compare channel 3 uart1 transmit data output address line 17 output p0.4 64/2 hi-z mtsr_1 cc62_1 txd1_0 a18 ssc master transmit output/ slave receive input input/output of capture/compare channel 2 uart1 transmit data output/clock output address line 18 output p0.5 1/3 hi-z mrst_1 exint0_0 t2ex1_1 rxd1_0 cout62_1 a19 ssc master receive input/slave transmit output external interrupt input 0 timer 21 external trigger input uart1 receive data input output of ca pture/compare channel 2 address line 19 output p0.6 2/4 pu t2cc4_1 wr compare output channel 4 external data write control output p0.7 62/48 pu clkout_1 t2cc5_1 rd clock output compare output channel 5 external data read control output table 3 pin definiti ons and functions (cont?d) symbol pin number (lqfp-64 / vqfn-48) type reset state function
xc87xclm general device information data sheet 12 v1.5, 2011-03 p1 i/o port 1 port 1 is an 8-bit bidi rectional general purpose i/o port. it can be used as alternate functions for the jtag, ccu6, uart, timer 0, timer 1, t2ccu, timer 21, multican, ssc and external bus interface. note: external bus interface is not available in xc874. p1.0 34/25 pu rxd_0 t2ex_0 rxdc0_0 a8 uart receive data input timer 2 external trigger input multican node 0 receiver input address line 8 output p1.1 35/26 pu exint3_0 t0_1 txd_0 txdc0_0 a9 external interrupt input 3 timer 0 input uart transmit data output/clock output multican node 0 transmitter output address line 9 output p1.2 36/27 pu sck_0 a10 ssc clock input/output address line 10 output p1.3 37/28 pu mtsr_0 sck_2 txdc1_3 a11 ssc master transmit output/slave receive input ssc clock input/output multican node 1 transmitter output address line 11 output p1.4 38/29 pu mrst_0 exint0_1 rxdc1_3 mtsr_2 a12 ssc master receive input/ slave transmit output external interrupt input 0 multican node 1 receiver input ssc master transmit output/slave receive input address line 12 output table 3 pin definiti ons and functions (cont?d) symbol pin number (lqfp-64 / vqfn-48) type reset state function
xc87xclm general device information data sheet 13 v1.5, 2011-03 p1.5 39/30 pu ccpos0_1 exint5_0 t1_1 mrst_2 exf2_0 rxdo_0 ccu6 hall input 0 external interrupt input 5 timer 1 input ssc master receive input/ slave transmit output timer 2 external flag output uart transmit data output p1.6 10/9 pu ccpos1_1 t12hr_0 exint6_0 rxdc0_2 t21_1 ccu6 hall input 1 ccu6 timer 12 hardware run input external interrupt input 6 multican node 0 receiver input timer 21 input p1.7 11/10 pu ccpos2_1 t13hr_0 t2_1 txdc0_2 ccu6 hall input 2 ccu6 timer 13 hardware run input timer 2 input multican node 0 transmitter output p1.5 and p1.6 can be us ed as a software chip select output for the ssc. table 3 pin definiti ons and functions (cont?d) symbol pin number (lqfp-64 / vqfn-48) type reset state function
xc87xclm general device information data sheet 14 v1.5, 2011-03 p3 i/o port 3 port 3 is an 8-bit bidi rectional general purpose i/o port. it can be used as alternate functions for ccu6, uart1, t2ccu, timer 21, multican and external bus interface. note: external bus interface is not available in xc874. p3.0 43/33 hi-z ccpos1_2 cc60_0 rxdo1_1 t2cc0_1/ exint3_2 ccu6 hall input 1 input/output of capture/compare channel 0 uart1 transmit data output external interrupt input 3/t2ccu capture/compare channel 0 p3.1 44/34 hi-z ccpos0_2 cc61_2 cout60_0 txd1_1 ccu6 hall input 0 input/output of capture/compare channel 1 output of ca pture/compare channel 0 uart1 transmit data output/clock output p3.2 49/35 hi-z ccpos2_2 rxdc1_1 rxd1_1 cc61_0 t2cc1_1/ exint4_2 ccu6 hall input 2 multican node 1 receiver input uart1 receive data input input/output of capture/compare channel 1 external interrupt input 4/t2ccu capture/compare channel 1 p3.3 50/36 hi-z cout61_0 txdc1_1 t2cc2_1/ exint5_2 a13 output of ca pture/compare channel 1 multican node 1 transmitter output external interrupt input 5/t2ccu capture/compare channel 2 address line 13 output table 3 pin definiti ons and functions (cont?d) symbol pin number (lqfp-64 / vqfn-48) type reset state function
xc87xclm general device information data sheet 15 v1.5, 2011-03 p3.4 51/37 hi-z cc62_0 rxdc0_1 t2ex1_0 t2cc3_1/ exint6_3 a14 input/output of capture/compare channel 2 multican node 0 receiver input timer 21 external trigger input external interrupt input 6/t2ccu capture/compare channel 3 address line 14 output p3.5 52/38 hi-z cout62_0 exf21_0 txdc0_1 a15 output of ca pture/compare channel 2 timer 21 external flag output multican node 0 transmitter output address line 15 output p3.6 41/32 pu ctrap_0 ccu6 trap input p3.7 42/- hi-z exint4_0 cout63_0 a16 external interrupt input 4 output of ca pture/compare channel 3 address line 16 output table 3 pin definiti ons and functions (cont?d) symbol pin number (lqfp-64 / vqfn-48) type reset state function
xc87xclm general device information data sheet 16 v1.5, 2011-03 p4 i/o port 4 port 4 is an 8-bit bidi rectional general purpose i/o port. it can be used as alternate functions for ccu6, timer 0, time r 1, t2ccu, timer 21, multican and external bus interface. note: external bus interface is not available in xc874. p4.0 59/45 hi-z rxdc0_3 cc60_1 t2cc0_0/ exint3_1 d0 multican node 0 receiver input output of ca pture/compare channel 0 external interrupt input 3/t2ccu capture/compare channel 0 data line 0 input/output p4.1 60/46 hi-z txdc0_3 cout60_1 t2cc1_0/ exint4_1 d1 multican node 0 transmitter output output of ca pture/compare channel 0 external interrupt input 4/t2ccu capture/compare channel 1 data line 1 input/output p4.2 61/47 pu exint6_1 t21_0 d2 external interrupt input 6 timer 21 input data line 2 input/output p4.3 40/31 hi-z t2ex_1 exf21_1 cout63_2 d3 timer 2 external trigger input timer 21 external flag output output of ca pture/compare channel 3 data line 3 input/output p4.4 45/- hi-z ccpos0_3 t0_0 cc61_4 t2cc2_0/ exint5_1 d4 ccu6 hall input 0 timer 0 input output of ca pture/compare channel 1 external interrupt input 5/t2ccu capture/compare channel 2 data line 4 input/output table 3 pin definiti ons and functions (cont?d) symbol pin number (lqfp-64 / vqfn-48) type reset state function
xc87xclm general device information data sheet 17 v1.5, 2011-03 p4.5 46/- hi-z ccpos1_3 t1_0 cout61_2 t2cc3_0/ exint6_2 d5 ccu6 hall input 1 timer 1 input output of ca pture/compare channel 1 external interrupt input 6/t2ccu capture/compare channel 3 data line 5 input/output p4.6 47/- hi-z ccpos2_3 t2_0 cc62_2 t2cc4_0 d6 ccu6 hall input 2 timer 2 input output of ca pture/compare channel 2 compare output channel 4 data line 6 input/output p4.7 48/- hi-z ctrap_3 cout62_2 t2cc5_0 d7 ccu6 trap input output of capture/compare channel 2 compare output channel 5 data line 7 input/output table 3 pin definiti ons and functions (cont?d) symbol pin number (lqfp-64 / vqfn-48) type reset state function
xc87xclm general device information data sheet 18 v1.5, 2011-03 p5 i/o port 5 port 5 is an 8-bit bidi rectional general purpose i/o port. it can be used as alternate functions for uart, uart1, t2ccu, jtag and external interface. p5.0 8/- pu exint1_1 a0 external interrupt input 1 address line 0 output p5.1 9/- pu exint2_1 a1 external interrupt input 2 address line 1 output p5.2 12/- pu rxd_2 t2cc2_2/ exint5_3 a2 uart receive data input external interrupt input 5/t2ccu capture/compare channel 2 address line 2 output p5.3 13/- pu ccpos0_0 exint1_0 t12hr_2 cc61_3 txd_2 t2cc5_2 a3 ccu6 hall input 0 external interrupt input 1 ccu6 timer 12 hardware run input input of capture/compare channel 1 uart transmit data output/clock output compare output channel 5 address line 3 output p5.4 14/- pu ccpos1_0 exint2_0 t13hr_2 cc62_3 rxdo_2 t2cc4_2 a4 ccu6 hall input 1 external interrupt input 2 ccu6 timer 13 hardware run input input of capture/compare channel 2 uart transmit data output compare output channel 4 address line 4 output table 3 pin definiti ons and functions (cont?d) symbol pin number (lqfp-64 / vqfn-48) type reset state function
xc87xclm general device information data sheet 19 v1.5, 2011-03 p5.5 15/- pu ccpos2_0 ctrap_1 cc60_3 tdo_1 txd1_2 t2cc0_2/ exint3_3 a5 ccu6 hall input 2 ccu6 trap input input of capture/compare channel 0 jtag serial data output uart1 transmit data output/ clock output external interrupt input 3/t2ccu capture/compare channel 0 address line 5 output p5.6 19/- pu tck_1 rxdo1_2 t2cc1_2/ exint4_3 a6 jtag clock input uart1 transmit data output external interrupt input 4/t2ccu capture/compare channel 1 address line 6 output p5.7 20/- pu tdi_1 rxd1_2 t2cc3_2/ exint6_4 a7 jtag serial data input uart1 receive data input external interrupt input 6/t2ccu capture/compare channel 3 address line 7 output table 3 pin definiti ons and functions (cont?d) symbol pin number (lqfp-64 / vqfn-48) type reset state function
xc87xclm general device information data sheet 20 v1.5, 2011-03 v ddp 7, 25, 55/ 17, 41 ?? i/o port supply (3.3 or 5.0 v) also used by evr and analog modules. all pins must be connected. v ssp 26, 54/ 18, 40 ?? i/o ground all pins must be connected. v ddc 6/8 ? ? core supply monitor (2.5 v) v ssc 5/7 ? ? core supply ground v aref 32/23 ? ? adc reference voltage v agnd 31/22 ? ? adc reference ground an0 22/- i hi-z analog input 0 an1 23/15 i hi-z analog input 1 an2 24/16 i hi-z analog input 2 an3 27/- i hi-z analog input 3 an4 28/19 i hi-z analog input 4 an5 29/20 i hi-z analog input 5 an6 30/21 i hi-z analog input 6 an7 33/24 i hi-z analog input 7 xtal1 4/6 i hi-z external oscillator input (feedback resistor required, normally nc) xtal2 3/5 o hi-z external oscillator output (feedback resistor required, normally nc) tms 16/11 i pd jtag test mode select reset 53/39 i pu reset input mbc 58/44 i pu monitor & bootstra p loader control tm 57/43 ? ? test mode (external pull down device required) nc 56/42 ? ? no connection table 3 pin definiti ons and functions (cont?d) symbol pin number (lqfp-64 / vqfn-48) type reset state function
xc87xclm functional description data sheet 21 v1.5, 2011-03 3 functional description chapter 3 provides an overview of t he xc87x functional description. 3.1 processor architecture the xc87x is based on a high -performance 8-bit central processing unit (cpu) that is compatible with the standar d 8051 processor. while t he standard 8051 processor is designed around a 12-clock ma chine cycle, the xc87x cpu uses a 2-clock machine cycle. this allows fast access to rom or ram memories without wait state. the instruction set consists of 45% one-byte, 41% two-byte and 14% three-byte instructions. the xc87x cpu provides a r ange of debugging features, including basic stop/start, single-step execution, break point support and r ead/write access to the data memory, program memory and special function registers (sfrs). figure 6 shows the cpu functional blocks. figure 6 cpu block diagram register interface alu uart core sfrs 16-bit registers & memory interface opcode decoder state machine & power saving interrupt controller multiplier / divider opcode & immediate registers timer 0 / timer 1 internal data memory external sfrs external data memory program memory f cclk memory wait reset legacy external interrupts (ien0, ien1) external interrupts non-maskable interrupt
xc87xclm functional description data sheet 22 v1.5, 2011-03 3.2 memory organization the xc87x cpu operates in t he following address spaces: ? 8 kbytes of boot rom program memory ? 256 bytes of intern al ram data memory ? 3 kbytes of xram memory (xram can be read/written as program memory or exter nal data memory) ? a 128-byte special function register area ? 64/52 kbytes of flash progr am memory (flash devices) figure 7 and figure 8 illustrate the memory addre ss spaces of the xc87x with 64kbytes and 52kbytes embedded flash respectively. figure 7 memory map of xc87x with 64k flash memory in user mode external external reserved data space 0' 0000 h xram 3 kbyte 0' ffff h f' f000 h f' fc00 h 1' 0000 h 1' ffff h 2' 0000 h 2' ffff h 3' 0000 h 3' ffff h 4' 0000 h 4' ffff h 5' 0000 h 5' ffff h 6' 0000 h 6' ffff h 7' 0000 h 7' ffff h 8' 0000 h 8' ffff h 9' 0000 h 9' ffff h a' 0000 h a' ffff h b' 0000 h b' ffff h c' 0000 h c' ffff h d' 0000 h d' ffff h e' 0000 h e' ffff h f' 0000 h f' ffff h external external 2' fe00 h reserved reserved reserved 2' c000 h 2' f000 h 2' fc00 h 2' fec0 h external external external 2' e000 h reserved 0' 0000 h 2' fe00 h p-flash 60 kbyte boot rom 8 kbyte xram 3 kbyte code space internal data space memor y map user mode d-flash 4 kbyte 0' ffff h reserved 0' f000 h 1' 0000 h 2' c000 h 2' f000 h 2' fc00 h 1' ffff h 2' 0000 h 2' ffff h 3' 0000 h 3' ffff h 4' 0000 h 4' ffff h 5' 0000 h 5' ffff h 6' 0000 h 6' ffff h 7' 0000 h 7' ffff h 8' 0000 h 8' ffff h 9' 0000 h 9' ffff h a' 0000 h a' ffff h b' 0000 h b' ffff h c' 0000 h c' ffff h d' 0000 h d' ffff h e' 0000 h e' ffff h f' 0000 h f' ffff h bank 1 bank 3 bank 4 bank 5 bank 6 bank 7 bank 8 bank 9 bank a bank b bank c bank d bank e bank 2 bank 0 2' fec0 h bank f reserved reserved reserved 2' e000 h extension stack ram memory extension stack pointer (mexsp) special function registers indirect address direct address 00 h internal ram 7f h internal ram 80 h ff h
xc87xclm functional description data sheet 23 v1.5, 2011-03 figure 8 memory map of xc87x with 52k flash memory in user mode external reserved external external 0000 h f000 h c000 h e000 h fc00 h ffff h 8000 h fe00 h reserved p-flash 32 kbyte p-flash 48 kbyte / d-flash 4 kbyte boot rom 8 kbyte xram 2 kbyte code space internal data space memory map user mode fec0 h reserved extension stack ram memory extension stack pointer (mexsp) special function registers indirect address direct address 00 h internal ram 7f h internal ram 80 h ff h f000 h fc00 h 0000 h ffff h data space xram 2 kbyte reserved external fe00 h reserved fec0 h external reserved / external c000 h 8000 h reserved 1'0000 h f?ffff h 1'0000 h f?ffff h
xc87xclm functional description data sheet 24 v1.5, 2011-03 3.2.1 memory protection strategy the xc87x memory protecti on strategy includes: ? basic protection: the user is able to block any extern al access via the boot option to any memory ? read-out protection: the user is able to protect the contents in the flash ? flash program and erase protection these protection strategies are enabled by programming a valid password (16-bit non- one value) via bootst rap loader (bsl) mode 6. 3.2.1.1 flash memory protection as long as a valid password is available, all external access to th e device, including the flash, will be blocked. for additional security, the flash hardware protection can be enabled to implement a second layer of read-out protection, as we ll as to enable progra m and erase protection. flash hardware protection is available only for flash devices and comes in two modes: ? mode 0: only the p-flash is prot ected; the d-flas h is unprotected ? mode 1: both the p-flash and d-flash are protected the selection of each prot ection mode and the restrictio ns imposed are summarized in table 4 . table 4 flash protection modes flash protection without hardware protection with hardware protection hardware protection mode -01 activation program a valid passwo rd via bsl mode 6 selection bit 13 of password = 0 bit 13 of password = 1 msb of password = 0 bit 13 of password = 1 msb of password = 1 p-flash contents can be read by read instructions in any program memory read instructions in the p-flash read instructions in the p-flash or d- flash external access to p- flash not possible not possible not possible
xc87xclm functional description data sheet 25 v1.5, 2011-03 bsl mode 6, which is used for enabling flash protection, can also be used for disabling flash protection. here, the programmed password must be provided by the user. to disable the flash protection, a password match is required. a password match triggers an automatic erase of the protected p-flash and d- flash contents, including the programmed password. with a valid passwor d, the flash hardware protection is then enabled or disabled upon next reset. for the other protec tion strategies, no reset is necessary. although no protection schem e can be considered infallible, the xc87x memory protection strategy provides a very high level of protec tion for a general purpose microcontroller. note: if rom read-out protection is enabled, only read inst ructions in the rom memory can target the rom contents. p-flash program and erase possible possible only on the condition that msb - 1 of password is set to 1 possible only on the condition that msb - 1 of password is set to 1 d-flash contents can be read by read instructions in any program memory read instructions in any program memory read instructions in the p-flash or d- flash external access to d- flash not possible not possible not possible d-flash program possible possible possible, on the condition that msb - 1 of password is set to 1 d-flash erase possible possible, on these conditions: ? misc_con.dflash en bit is set to 1 prior to each erase operation; or ? the msb - 1 of password is set to 1 possible, on the condition that msb - 1 of password is set to 1 table 4 flash protection modes (cont?d) flash protection without hardware protection with hardware protection
xc87xclm functional description data sheet 26 v1.5, 2011-03 3.2.2 special function register the special function regi sters (sfrs) occupy direct inte rnal data memory space in the range 80 h to ff h . all registers, except the program co unter, reside in the sfr area. the sfrs include pointers and r egisters that provide an inte rface between t he cpu and the on-chip peripherals. as the 128-sfr range is less than th e total number of registers required, address extension mechanisms ar e required to increa se the number of addressable sfrs. t he address extension mechanisms include: ? mapping ?paging 3.2.2.1 address extension by mapping address extension is performed at the syst em level by mapping. the sfr area is extended into two portions: the standard (non-mapped) sf r area and the mapped sfr area. each portion supports the same address range 80 h to ff h , bringing the number of addressable sfrs to 256. t he extended address rang e is not directly controlled by the cpu instruction itself, but is derived from bi t rmap in the system control register syscon0 at address 8f h . to access sfrs in the mapped area, bit rmap in sfr syscon0 must be set. alternatively, the sfrs in the standar d area can be accessed by clearing bit rmap. the sfr area can be selected as shown in figure 9 . as long as bit rmap is set, the mapped sfr area can be accessed. this bit is not cleared automatically by hardware. thus , before standard/ma pped registers are accessed, bit rmap must be cleared/set, resp ectively, by software.
xc87xclm functional description data sheet 27 v1.5, 2011-03 figure 9 address extension by mapping module 1 sfrs ?... syscon0.rmap sfr data (to/from cpu) rw standard area (rmap = 0) ?... 80 h ff h 80 h ff h direct internal data memory address mapped area (rmap = 1) module 2 sfrs module n sfrs module (n+1) sfrs module (n+2) sfrs module m sfrs
xc87xclm functional description data sheet 28 v1.5, 2011-03 note: the rmap bit should be cl eared/set by anl or orl in structions.the rest bits of syscon0 should no t be modified. 3.2.2.2 address extension by paging address extension is further performed at the m odule level by paging. with the address extension by mapping, the xc87x has a 256-s fr address range. howe ver, this is still less than the total number of sfrs needed by the on-chi p peripherals. to meet this requirement, some peripherals have a built-i n local address extens ion mechanism for increasing the number of addressable sfrs. the extend ed address range is not directly controlled by the cpu instruction itself, but is derived from bit fi eld page in the module page register mod_page. hence, the bi t field page must be programmed before accessing the sfr of the target module. each module may contai n a different number of pages and a different number of sf rs per page, dependi ng on the specific requirement. besides setting the correct rmap bit value to select the sfr area, the user must also ensure that a valid page is select ed to target the desired sfr. a page inside the extended address range can be select ed as shown in figure 10 . syscon0 system control register 0 reset value: 04 h 76543210 0 imode 0 1 0 rmap r rwrrrrw field bits type description rmap 0rw interrupt node xintr0 enable 0 the access to the st andard sfr area is enabled 1 the access to the m apped sfr area is enabled 1 2r reserved returns 1 if re ad; should be written with 1. 0 [7:5], 3,1 r reserved returns 0 if re ad; should be written with 0.
xc87xclm functional description data sheet 29 v1.5, 2011-03 figure 10 address extension by paging in order to access a register located in a pag e different from the actual o ne, the current page must be exited. this is done by reprog ramming the bit fi eld page in the page register. only then can th e desired access be performed. if an interrupt routine is initiated be tween the page register access and the module register access, and t he interrupt needs to access a regist er located in another page, the current page setting can be saved, the new one programm ed and the old page setting restored. this is possible with the storage fields stx (x = 0 - 3) for the save and restore action of the current page setting. by indicating which st orage bit field should be used in parallel with t he new page value, a sing le write operation can: ? save the contents of page in stx be fore overwriting with the new value (this is done in th e beginning of the interrupt routi ne to save the current page setting and program the new page number); or sfr0 sfr1 sfrx ?... page 0 sfr0 sfr1 sfry ?... page 1 ?... sfr0 sfr1 sfrz ?... page q mod_page.page sfr address (from cpu) sfr data (to/from cpu) rw module
xc87xclm functional description data sheet 30 v1.5, 2011-03 ? overwrite the contents of page with the co ntents of stx, ignori ng the value written to the bit positions of page (this is done at the end of the interrupt ro utine to restore the previous page setting before the interrupt occurred) figure 11 storage elements for paging with this mechanism, a certain number of interrupt routines (or other routines) can perform page changes without reading and stor ing the previously used page information. the use of only write oper ations makes the system simp ler and faster. consequently, this mechanism significantly improves the performance of short interrupt routines. the xc87x supports loca l address extension for: ? parallel ports ? analog-to-digital converter (adc) ? capture/compare unit 6 (ccu6) ? system control registers page st0 st1 st2 st3 value update from cpu stnr
xc87xclm functional description data sheet 31 v1.5, 2011-03 the page register has th e following definition: mod_page page register for modu le mod reset value: 00 h 76543210 op stnr 0 page wwrrw field bits type description page [2:0] rw page bits when written, the value indicates the new page. when read, the value indica tes the currently active page. stnr [5:4] w storage number this number indicates whic h storage bit field is the target of the operation defined by bit field op. if op = 10 b , the contents of page are saved in stx before being overwritten with the new value. if op = 11 b , the contents of page are overwritten by the contents of stx. the value written to the bit positions of page is ignored. 00 st0 is selected. 01 st1 is selected. 10 st2 is selected. 11 st3 is selected.
xc87xclm functional description data sheet 32 v1.5, 2011-03 3.2.3 bit protection scheme the bit protection scheme prevents direct software wr iting of selected bi ts (i.e., protected bits) using the passwd re gister. when the bi t field mode is 11 b , writing 10011 b to the bit field pass opens access to writing of all protect ed bits, and writing 10101 b to the bit field pass closes access to writing of all prot ected bits. in both case s, the value of the bit field mode is not changed even if passwd regi ster is written with 98 h or a8 h . it can only be changed wh en bit field pass is written with 11000 b , for example, writing d0 h to passwd register disables th e bit protec tion scheme. note that access is opened fo r maximum 32 cclks if the ?clo se access? password is not written. if ?open access? password is wr itten again before the end of 32 cclk cycles, there will be a recount of 32 cclk cycles. the protecte d bits include the n- and k- divider bits, ndiv and kdiv; the watchdog timer enable bit, wdten; and the power- down and slow-down en able bits, pd and sd. op [7:6] w operation 0x manual page mode. th e value of stnr is ignored and page is directly written. 10 new page programming with automatic page saving. the value written to the bit positions of page is stored. in pa rallel, the previous contents of page are save d in the storage bit field stx indicated by stnr. 11 automatic restore page action. the value written to the bit positions page is ignored and instead, page is overwritten by the contents of the storage bit field stx indicated by stnr. 0 3r reserved returns 0 if re ad; should be written with 0. field bits type description
xc87xclm functional description data sheet 33 v1.5, 2011-03 3.2.3.1 password register passwd password register reset value: 07 h 76543210 pass protect _s mode wrhrw field bits type description mode [1:0] rw bit protection scheme control bits 00 scheme disabled - di rect access to the protected bits is allowed. 11 scheme enabled - the bi t field pass has to be written with the passwor ds to open and close the access to prot ected bits. (default) others:scheme enabled. these two bits cannot be written directly. to change the value between 11 b and 00 b , the bit field pass must be written with 11000 b ; only then, will the mode[1:0] be registered. protect_s 2rh bit protection signal status bit this bit shows the stat us of the protection. 0 software is able to writ e to all protected bits. 1 software is unable to write to any protected bits. pass [7:3] w password bits the bit protection scheme only reco gnizes three patterns. 11000 b enables writing of the bit field mode. 10011 b opens access to writing of all protected bits. 10101 b closes access to writin g of all protected bits
xc87xclm functional description data sheet 34 v1.5, 2011-03 3.2.4 xc87x register overview the sfrs of the xc87x are organized into gr oups according to thei r functional units. the contents (bits) of the sfrs are summarized in chapter 3.2.4.1 to chapter 3.2.4.15 . note: the addresses of th e bitaddressable sfrs ap pear in bold typeface. 3.2.4.1 cpu registers the cpu sfrs can be accessed in both the standard and ma pped memory areas (rmap = 0 or 1). table 5 cpu register overview addr register name bit 7 6 5 4 3 2 1 0 rmap = 0 or 1 81 h sp reset: 07 h stack pointer register bit field sp type rw 82 h dpl reset: 00 h data pointer register low bit field dpl7 dpl6 dpl5 dpl4 dpl3 dpl2 dpl1 dpl0 type rw rw rw rw rw rw rw rw 83 h dph reset: 00 h data pointer register high bit field dph7 dph6 dph5 dph4 dph3 dph2 dph1 dph0 type rw rw rw rw rw rw rw rw 87 h pcon reset: 00 h power control register bit field smod 0 gf1 gf0 0 idle type rw r rw rw r rw 88 h tcon reset: 00 h timer control register bit field tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 type rwh rw rwh rw rwh rw rwh rw 89 h tmod reset: 00 h timer mode register bit field gate 1 t1s t1m gate 0 t0s t0m type rw rw rw rw rw rw 8a h tl0 reset: 00 h timer 0 register low bit field val type rwh 8b h tl1 reset: 00 h timer 1 register low bit field val type rwh 8c h th0 reset: 00 h timer 0 register high bit field val type rwh 8d h th1 reset: 00 h timer 1 register high bit field val type rwh 94 h mex1 reset: 00 h memory extension register 1 bit field cb nb type r rw 95 h mex2 reset: 00 h memory extension register 2 bit field mcm mcb ib type rw rw rw 96 h mex3 reset: 00 h memory extension register 3 bit field mcb1 9 0 mxb1 9 mxm mxb type rw r rw rw rw
xc87xclm functional description data sheet 35 v1.5, 2011-03 3.2.4.2 mdu registers the mdu sfrs can be accessed in the mapped memory area (rmap = 1). 97 h mexsp reset: 7f h memory extension stack pointer register bit field 0 mxsp type r rwh 98 h scon reset: 00 h serial channel control register bit field sm0 sm1 sm2 ren tb8 rb8 ti ri type rw rw rw rw rw rwh rwh rwh 99 h sbuf reset: 00 h serial data buffer register bit field val type rwh a2 h eo reset: 00 h extended operation register bit field 0 trap_ en 0 dpse l0 type r rw r rw a8 h ien0 reset: 00 h interrupt enable register 0 bit field ea 0 et2 es et1 ex1 et0 ex0 type rw r rwrwrwrwrwrw b8 h ip reset: 00 h interrupt priority register bit field 0 pt2 ps pt1 px1 pt0 px0 type r rwrwrwrwrwrw b9 h iph reset: 00 h interrupt priority high register bit field 0 pt2h psh pt1h px1h pt0h px0h type r rwrwrwrwrwrw d0 h psw reset: 00 h program status word register bit field cy ac f0 rs1 rs0 ov f1 p type rwh rwh rw rw rw rwh rw rh e0 h acc reset: 00 h accumulator register bit field acc7 acc6 acc5 acc4 acc3 acc2 acc1 acc0 type rw rw rw rw rw rw rw rw e8 h ien1 reset: 00 h interrupt enable register 1 bit field eccip 3 eccip 2 eccip 1 eccip 0 exm ex2 essc eadc type rw rw rw rw rw rw rw rw f0 h b reset: 00 h b register bit field b7 b6 b5 b4 b3 b2 b1 b0 type rw rw rw rw rw rw rw rw f8 h ip1 reset: 00 h interrupt priority 1 register bit field pccip 3 pccip 2 pccip 1 pccip 0 pxm px2 pssc padc type rw rw rw rw rw rw rw rw f9 h iph1 reset: 00 h interrupt priority 1 high register bit field pccip 3h pccip 2h pccip 1h pccip 0h pxmh px2h pssc h padc h type rw rw rw rw rw rw rw rw table 6 mdu register overview addr register name bit 7 6 5 4 3 2 1 0 rmap = 1 b0 h mdustat reset: 00 h mdu status register bit field 0 bsy ierr irdy type r rh rwh rwh table 5 cpu register overview (cont?d) addr register name bit 7 6 5 4 3 2 1 0
xc87xclm functional description data sheet 36 v1.5, 2011-03 3.2.4.3 cordic registers the cordic sfrs can be accessed in the mapped memory area (rmap = 1). b1 h mducon reset: 00 h mdu control register bit field ie ir rsel star t opcode type rw rw rw rwh rw b2 h md0 reset: 00 h mdu operand register 0 bit field data type rw b2 h mr0 reset: 00 h mdu result register 0 bit field data type rh b3 h md1 reset: 00 h mdu operand register 1 bit field data type rw b3 h mr1 reset: 00 h mdu result register 1 bit field data type rh b4 h md2 reset: 00 h mdu operand register 2 bit field data type rw b4 h mr2 reset: 00 h mdu result register 2 bit field data type rh b5 h md3 reset: 00 h mdu operand register 3 bit field data type rw b5 h mr3 reset: 00 h mdu result register 3 bit field data type rh b6 h md4 reset: 00 h mdu operand register 4 bit field data type rw b6 h mr4 reset: 00 h mdu result register 4 bit field data type rh b7 h md5 reset: 00 h mdu operand register 5 bit field data type rw b7 h mr5 reset: 00 h mdu result register 5 bit field data type rh table 7 cordic register overview addr register name bit 7 6 5 4 3 2 1 0 rmap = 1 9a h cd_cordxl reset: 00 h cordic x data low byte bit field datal type rw 9b h cd_cordxh reset: 00 h cordic x data high byte bit field datah type rw table 6 mdu register overview (cont?d) addr register name bit 7 6 5 4 3 2 1 0
xc87xclm functional description data sheet 37 v1.5, 2011-03 3.2.4.4 system control registers the system control sfrs can be accessed in the mapped memory area (rmap = 0). 9c h cd_cordyl reset: 00 h cordic y data low byte bit field datal type rw 9d h cd_cordyh reset: 00 h cordic y data high byte bit field datah type rw 9e h cd_cordzl reset: 00 h cordic z data low byte bit field datal type rw 9f h cd_cordzh reset: 00 h cordic z data high byte bit field datah type rw a0 h cd_statc reset: 00 h cordic status and data control register bit field keep z keep y keep x dmap int_e n eoc erro r bsy type rw rw rw rw rw rwh rh rh a1 h cd_con reset: 00 h cordic control register bit field mps x_usi gn st_m ode rotv ec mode st type rw rw rw rw rw rwh table 8 scu register overview addr register name bit 7 6 5 4 3 2 1 0 rmap = 0 or 1 8f h syscon0 reset: 04 h system control register 0 bit field 0 imod e 0 1 0 rmap type r rw r r r rw rmap = 0 bf h scu_page reset: 00 h page register bit field op stnr 0 page type w w r rwh rmap = 0, page 0 b3 h modpisel reset: 00 h peripheral input select register bit field 0 urris h jtagt dis jtagt cks exint 2is exint 1is exint 0is urris type r rwrwrwrwrwrwrw b4 h ircon0 reset: 00 h interrupt request register 0 bit field 0 exint 6 exint 5 exint 4 exint 3 exint 2 exint 1 exint 0 type r rwh rwh rwh rwh rwh rwh rwh b5 h ircon1 reset: 00 h interrupt request register 1 bit field 0 cans rc2 cans rc1 adcs r1 adcs r0 rir tir eir type r rwh rwh rwh rwh rwh rwh rwh b6 h ircon2 reset: 00 h interrupt request register 2 bit field 0 cans rc3 0 cans rc0 type rrwhrrwh table 7 cordic register overview (cont?d) addr register name bit 7 6 5 4 3 2 1 0
xc87xclm functional description data sheet 38 v1.5, 2011-03 b7 h exicon0 reset: f0 h external interrupt control register 0 bit field exint3 exint2 exint1 exint0 type rw rw rw rw ba h exicon1 reset: 3f h external interrupt control register 1 bit field 0 exint6 exint5 exint4 typer rwrwrw bb h nmicon reset: 00 h nmi control register bit field 0 nmi ecc nmi vddp 0 nmi ocds nmi flash nmi pll nmi wdt type r rw rw r rw rw rw rw bc h nmisr reset: 00 h nmi status register bit field 0 fnmi ecc fnmi vddp 0 fnmi ocds fnmi flash fnmi pll fnmi wdt type r rwh rwh r rwh rwh rwh rwh bd h bcon reset: 20 h baud rate control register bit field bgsel ndov en brdis brpre r type rw rw rw rw rw be h bg reset: 00 h baud rate timer/reload register bit field br_value type rwh e9 h fdcon reset: 00 h fractional divider control register bit field bgs syne n errs yn eofs yn brk ndov fdm fden type rw rw rwh rwh rwh rwh rw rw ea h fdstep reset: 00 h fractional divider reload register bit field step type rw eb h fdres reset: 00 h fractional divider result register bit field result type rh rmap = 0, page 1 b3 h id reset: 49 h identity register bit field prodid verid type r r b4 h pmcon0 reset: 80 h power mode control register 0 bit field vddp warn wdt rst wkrs wk sel sd pd ws type rh rwh rwh rw rw rwh rw b5 h pmcon1 reset: 00 h power mode control register 1 bit field 0 cdc_ dis can_ dis mdu_ dis t2cc u_dis ccu_ dis ssc_ dis adc_ dis type r rwrwrwrwrwrwrw b6 h osc_con reset: xx h osc control register bit field pllrd res pllby p pllpd 0 xpd osc ss eord res exto scr type rwh rwh rw r rw rwh rwh rh b7 h pll_con reset: 18 h pll control register bit field ndiv pllr pll_l ock type rw rh rh ba h cmcon reset: 10 h clock control register bit field kdiv 0 fccf g clkrel type rw r rw rw table 8 scu register overview (cont?d) addr register name bit 7 6 5 4 3 2 1 0
xc87xclm functional description data sheet 39 v1.5, 2011-03 bb h passwd reset: 07 h password register bit field pass prot ect_s mode type w rh rw be h cocon reset: 00 h clock output control register bit field couts tlen 0 corel type rw rw r rw e9 h misc_con reset: 00 h miscellaneous control register bit field adce tr0_ mux adce tr1_ mux 0 dflas hen type rw rw r rwh ea h pll_con1 reset: 20 h pll control register 1 bit field ndiv pdiv type rw rw eb h cr_misc reset: 00 h or 01 h reset status register bit field cccf g mduc cfg ccuc cfg t2ccf g 0 hdrs t type rw rw rw rw r rwh rmap = 0, page 3 b3 h xaddrh reset: f0 h on-chip xram address higher order bit field addrh type rw b4 h ircon3 reset: 00 h interrupt request register 3 bit field 0 cans rc5 ccu6 sr1 0 cans rc4 ccu6 sr0 type r rwh rwh r rwh rwh b5 h ircon4 reset: 00 h interrupt request register 4 bit field 0 cans rc7 ccu6 sr3 0 cans rc6 ccu6 sr2 type r rwh rwh r rwh rwh b6 h modien reset: 07 h peripheral interrupt enable register bit field 0 cm5e n cm4e n riren tiren eiren type r rw rw rw rw rw b7 h modpisel1 reset: 00 h peripheral input select register 1 bit field exint6is ur1ris t21ex is 0 type rw rw rw r ba h modpisel2 reset: 00 h peripheral input select register 2 bit field 0 t2exi s t21is t2is t1is t0is type r rw rw rw rw rw bb h pmcon2 reset: 00 h power mode control register 2 bit field 0 uart 1_dis t21_d is type r rw rw bd h modsusp reset: 01 h module suspend control register bit field 0 ccts usp t21su sp t2sus p t13su sp t12su sp wdts usp type r rwrwrwrwrwrw be h modpisel3 reset: 00 h peripheral input select register 3 bit field 0 cis sis mis typer rwrwrw ea h modpisel4 reset: 00 h peripheral input select register 4 bit field 0 exint5is exint4is exint3is typer rwrwrw table 8 scu register overview (cont?d) addr register name bit 7 6 5 4 3 2 1 0
xc87xclm functional description data sheet 40 v1.5, 2011-03 3.2.4.5 wdt registers the wdt sfrs can be accessed in the mapped memory area (rmap = 1). 3.2.4.6 port registers the port sfrs can be accessed in the standard memory area (rmap = 0). table 9 wdt register overview addr register name bit 7 6 5 4 3 2 1 0 rmap = 1 bb h wdtcon reset: 00 h watchdog timer control register bit field 0 winb en wdtp r 0 wdte n wdtr s wdti n type r rw rh r rw rwh rw bc h wdtrel reset: 00 h watchdog timer reload register bit field wdtrel type rw bd h wdtwinb reset: 00 h watchdog window-boundary count register bit field wdtwinb type rw be h wdtl reset: 00 h watchdog timer register low bit field wdt type rh bf h wdth reset: 00 h watchdog timer register high bit field wdt type rh table 10 port register overview addr register name bit 7 6 5 4 3 2 1 0 rmap = 0 b2 h port_page reset: 00 h page register bit field op stnr 0 page type w w r rwh rmap = 0, page 0 80 h p0_data reset: 00 h p0 data register bit field p7 p6 p5 p4 p3 p2 p1 p0 type rwhrwhrwhrwhrwhrwhrwhrwh 86 h p0_dir reset: 00 h p0 direction register bit field p7 p6 p5 p4 p3 p2 p1 p0 type rw rw rw rw rw rw rw rw 90 h p1_data reset: 00 h p1 data register bit field p7 p6 p5 p4 p3 p2 p1 p0 type rwhrwhrwhrwhrwhrwhrwhrwh 91 h p1_dir reset: 00 h p1 direction register bit field p7 p6 p5 p4 p3 p2 p1 p0 type rw rw rw rw rw rw rw rw 92 h p5_data reset: 00 h p5 data register bit field p7 p6 p5 p4 p3 p2 p1 p0 type rwhrwhrwhrwhrwhrwhrwhrwh 93 h p5_dir reset: 00 h p5 direction register bit field p7 p6 p5 p4 p3 p2 p1 p0 type rw rw rw rw rw rw rw rw
xc87xclm functional description data sheet 41 v1.5, 2011-03 b0 h p3_data reset: 00 h p3 data register bit field p7 p6 p5 p4 p3 p2 p1 p0 type rwhrwhrwhrwhrwhrwhrwhrwh b1 h p3_dir reset: 00 h p3 direction register bit field p7 p6 p5 p4 p3 p2 p1 p0 type rw rw rw rw rw rw rw rw c8 h p4_data reset: 00 h p4 data register bit field p7 p6 p5 p4 p3 p2 p1 p0 type rwhrwhrwhrwhrwhrwhrwhrwh c9 h p4_dir reset: 00 h p4 direction register bit field p7 p6 p5 p4 p3 p2 p1 p0 type rw rw rw rw rw rw rw rw rmap = 0, page 1 80 h p0_pudsel reset: ff h p0 pull-up/pull-down select register bit field p7 p6 p5 p4 p3 p2 p1 p0 type rw rw rw rw rw rw rw rw 86 h p0_puden reset: c4 h p0 pull-up/pull- down enable register bit field p7 p6 p5 p4 p3 p2 p1 p0 type rw rw rw rw rw rw rw rw 90 h p1_pudsel reset: ff h p1 pull-up/pull-down select register bit field p7 p6 p5 p4 p3 p2 p1 p0 type rw rw rw rw rw rw rw rw 91 h p1_puden reset: ff h p1 pull-up/pull- down enable register bit field p7 p6 p5 p4 p3 p2 p1 p0 type rw rw rw rw rw rw rw rw 92 h p5_pudsel reset: ff h p5 pull-up/pull-down select register bit field p7 p6 p5 p4 p3 p2 p1 p0 type rw rw rw rw rw rw rw rw 93 h p5_puden reset: ff h p5 pull-up/pull- down enable register bit field p7 p6 p5 p4 p3 p2 p1 p0 type rw rw rw rw rw rw rw rw b0 h p3_pudsel reset: bf h p3 pull-up/pull-down select register bit field p7 p6 p5 p4 p3 p2 p1 p0 type rw rw rw rw rw rw rw rw b1 h p3_puden reset: 40 h p3 pull-up/pull- down enable register bit field p7 p6 p5 p4 p3 p2 p1 p0 type rw rw rw rw rw rw rw rw c8 h p4_pudsel reset: ff h p4 pull-up/pull-down select register bit field p7 p6 p5 p4 p3 p2 p1 p0 type rw rw rw rw rw rw rw rw c9 h p4_puden reset: 04 h p4 pull-up/pull- down enable register bit field p7 p6 p5 p4 p3 p2 p1 p0 type rw rw rw rw rw rw rw rw rmap = 0, page 2 80 h p0_altsel0 reset: 00 h p0 alternate select 0 register bit field p7 p6 p5 p4 p3 p2 p1 p0 type rw rw rw rw rw rw rw rw 86 h p0_altsel1 reset: 00 h p0 alternate select 1 register bit field p7 p6 p5 p4 p3 p2 p1 p0 type rw rw rw rw rw rw rw rw 90 h p1_altsel0 reset: 00 h p1 alternate select 0 register bit field p7 p6 p5 p4 p3 p2 p1 p0 type rw rw rw rw rw rw rw rw table 10 port register overview (cont?d) addr register name bit 7 6 5 4 3 2 1 0
xc87xclm functional description data sheet 42 v1.5, 2011-03 91 h p1_altsel1 reset: 00 h p1 alternate select 1 register bit field p7 p6 p5 p4 p3 p2 p1 p0 type rw rw rw rw rw rw rw rw 92 h p5_altsel0 reset: 00 h p5 alternate select 0 register bit field p7 p6 p5 p4 p3 p2 p1 p0 type rw rw rw rw rw rw rw rw 93 h p5_altsel1 reset: 00 h p5 alternate select 1 register bit field p7 p6 p5 p4 p3 p2 p1 p0 type rw rw rw rw rw rw rw rw b0 h p3_altsel0 reset: 00 h p3 alternate select 0 register bit field p7 p6 p5 p4 p3 p2 p1 p0 type rw rw rw rw rw rw rw rw b1 h p3_altsel1 reset: 00 h p3 alternate select 1 register bit field p7 p6 p5 p4 p3 p2 p1 p0 type rw rw rw rw rw rw rw rw c8 h p4_altsel0 reset: 00 h p4 alternate select 0 register bit field p7 p6 p5 p4 p3 p2 p1 p0 type rw rw rw rw rw rw rw rw c9 h p4_altsel1 reset: 00 h p4 alternate select 1 register bit field p7 p6 p5 p4 p3 p2 p1 p0 type rw rw rw rw rw rw rw rw rmap = 0, page 3 80 h p0_od reset: 00 h p0 open drain control register bit field p7 p6 p5 p4 p3 p2 p1 p0 type rw rw rw rw rw rw rw rw 86 h p0_ds reset: ff h p0 drive strength control register bit field p7 p6 p5 p4 p3 p2 p1 p0 type rw rw rw rw rw rw rw rw 90 h p1_od reset: 00 h p1 open drain control register bit field p7 p6 p5 p4 p3 p2 p1 p0 type rw rw rw rw rw rw rw rw 91 h p1_ds reset: ff h p1 drive strength control register bit field p7 p6 p5 p4 p3 p2 p1 p0 type rw rw rw rw rw rw rw rw 92 h p5_od reset: 00 h p5 open drain control register bit field p7 p6 p5 p4 p3 p2 p1 p0 type rw rw rw rw rw rw rw rw 93 h p5_ds reset: ff h p5 drive strength control register bit field p7 p6 p5 p4 p3 p2 p1 p0 type rw rw rw rw rw rw rw rw b0 h p3_od reset: 00 h p3 open drain control register bit field p7 p6 p5 p4 p3 p2 p1 p0 type rw rw rw rw rw rw rw rw b1 h p3_ds reset: ff h p3 drive strength control register bit field p7 p6 p5 p4 p3 p2 p1 p0 type rw rw rw rw rw rw rw rw c8 h p4_od reset: 00 h p4 open drain control register bit field p7 p6 p5 p4 p3 p2 p1 p0 type rw rw rw rw rw rw rw rw c9 h p4_ds reset: ff h p4 drive strength control register bit field p7 p6 p5 p4 p3 p2 p1 p0 type rw rw rw rw rw rw rw rw table 10 port register overview (cont?d) addr register name bit 7 6 5 4 3 2 1 0
xc87xclm functional description data sheet 43 v1.5, 2011-03 3.2.4.7 adc registers the adc sfrs can be accessed in t he standard memory area (rmap = 0). table 11 adc register overview addrregister name bit 76543210 rmap = 0 d1 h adc_page reset: 00 h page register bit field op stnr 0 page type w w r rw rmap = 0, page 0 ca h adc_globctr reset: 30 h global control register bit field anon dw ctc 0 type rw rw rw r cb h adc_globstr reset: 00 h global status register bit field 0 chnr 0 samp le busy type r rh r rh rh cc h adc_prar reset: 00 h priority and arbitration register bit field asen 1 asen 0 0 arbm csm1 prio1 csm0 prio0 type rw rw r rw rw rw rw rw cd h adc_lcbr reset: b7 h limit check boundary register bit field bound1 bound0 type rw rw ce h adc_inpcr0 reset: 00 h input class 0 register bit field stc type rw cf h adc_etrcr reset: 00 h external trigger control register bit field syne n1 syne n0 etrsel1 etrsel0 type rw rw rw rw rmap = 0, page 1 ca h adc_chctr0 reset: 00 h channel control register 0 bit field 0 lcc 0 resrsel type r rw r rw cb h adc_chctr1 reset: 00 h channel control register 1 bit field 0 lcc 0 resrsel type r rw r rw cc h adc_chctr2 reset: 00 h channel control register 2 bit field 0 lcc 0 resrsel type r rw r rw cd h adc_chctr3 reset: 00 h channel control register 3 bit field 0 lcc 0 resrsel type r rw r rw ce h adc_chctr4 reset: 00 h channel control register 4 bit field 0 lcc 0 resrsel type r rw r rw cf h adc_chctr5 reset: 00 h channel control register 5 bit field 0 lcc 0 resrsel type r rw r rw d2 h adc_chctr6 reset: 00 h channel control register 6 bit field 0 lcc 0 resrsel type r rw r rw d3 h adc_chctr7 reset: 00 h channel control register 7 bit field 0 lcc 0 resrsel type r rw r rw
xc87xclm functional description data sheet 44 v1.5, 2011-03 rmap = 0, page 2 ca h adc_resr0l reset: 00 h result register 0 low bit field result 0 vf drc chnr type rh r rh rh rh cb h adc_resr0h reset: 00 h result register 0 high bit field result type rh cc h adc_resr1l reset: 00 h result register 1 low bit field result 0 vf drc chnr type rh r rh rh rh cd h adc_resr1h reset: 00 h result register 1 high bit field result type rh ce h adc_resr2l reset: 00 h result register 2 low bit field result 0 vf drc chnr type rh r rh rh rh cf h adc_resr2h reset: 00 h result register 2 high bit field result type rh d2 h adc_resr3l reset: 00 h result register 3 low bit field result 0 vf drc chnr type rh r rh rh rh d3 h adc_resr3h reset: 00 h result register 3 high bit field result type rh rmap = 0, page 3 ca h adc_resra0l reset: 00 h result register 0, view a low bit field result vf drc chnr type rh rh rh rh cb h adc_resra0h reset: 00 h result register 0, view a high bit field result type rh cc h adc_resra1l reset: 00 h result register 1, view a low bit field result vf drc chnr type rh rh rh rh cd h adc_resra1h reset: 00 h result register 1, view a high bit field result type rh ce h adc_resra2l reset: 00 h result register 2, view a low bit field result vf drc chnr type rh rh rh rh cf h adc_resra2h reset: 00 h result register 2, view a high bit field result type rh d2 h adc_resra3l reset: 00 h result register 3, view a low bit field result vf drc chnr type rh rh rh rh d3 h adc_resra3h reset: 00 h result register 3, view a high bit field result type rh rmap = 0, page 4 ca h adc_rcr0 reset: 00 h result control register 0 bit field vfct r wfr 0 ien 0 drct r type rw rw r rw r rw table 11 adc register overview (cont?d) addrregister name bit 76543210
xc87xclm functional description data sheet 45 v1.5, 2011-03 cb h adc_rcr1 reset: 00 h result control register 1 bit field vfct r wfr 0 ien 0 drct r type rw rw r rw r rw cc h adc_rcr2 reset: 00 h result control register 2 bit field vfct r wfr 0 ien 0 drct r type rw rw r rw r rw cd h adc_rcr3 reset: 00 h result control register 3 bit field vfct r wfr 0 ien 0 drct r type rw rw r rw r rw ce h adc_vfcr reset: 00 h valid flag clear register bit field 0 vfc3 vfc2 vfc1 vfc0 type r w w w w rmap = 0, page 5 ca h adc_chinfr reset: 00 h channel interrupt flag register bit field chinf 7 chinf 6 chinf 5 chinf 4 chinf 3 chinf 2 chinf 1 chinf 0 type rh rh rh rh rh rh rh rh cb h adc_chincr reset: 00 h channel interrupt clear register bit field chinc 7 chinc 6 chinc 5 chinc 4 chinc 3 chinc 2 chinc 1 chinc 0 typewwwwwwww cc h adc_chinsr reset: 00 h channel interrupt set register bit field chins 7 chins 6 chins 5 chins 4 chins 3 chins 2 chins 1 chins 0 typewwwwwwww cd h adc_chinpr reset: 00 h channel interrupt node pointer register bit field chinp 7 chinp 6 chinp 5 chinp 4 chinp 3 chinp 2 chinp 1 chinp 0 type rw rw rw rw rw rw rw rw ce h adc_evinfr reset: 00 h event interrupt flag register bit field evinf 7 evinf 6 evinf 5 evinf 4 0 evinf 1 evinf 0 type rh rh rh rh r rh rh cf h adc_evincr reset: 00 h event interrupt clear flag register bit field evinc 7 evinc 6 evinc 5 evinc 4 0 evinc 1 evinc 0 typewwww r ww d2 h adc_evinsr reset: 00 h event interrupt set flag register bit field evins 7 evins 6 evins 5 evins 4 0 evins 1 evins 0 typewwww r ww d3 h adc_evinpr reset: 00 h event interrupt node pointer register bit field evinp 7 evinp 6 evinp 5 evinp 4 0 evinp 1 evinp 0 type rw rw rw rw r rw rw rmap = 0, page 6 ca h adc_crcr1 reset: 00 h conversion request control register 1 bit field ch7 ch6 ch5 ch4 0 type rwh rwh rwh rwh r cb h adc_crpr1 reset: 00 h conversion request pending register 1 bit field chp7 chp6 chp5 chp4 0 type rwh rwh rwh rwh r table 11 adc register overview (cont?d) addrregister name bit 76543210
xc87xclm functional description data sheet 46 v1.5, 2011-03 cc h adc_crmr1 reset: 00 h conversion request mode register 1 bit field rsv ldev clrp nd scan ensi entr 0 engt type r w w rw rw rw r rw cd h adc_qmr0 reset: 00 h queue mode register 0 bit field cev trev flus h clrv 0 entr 0 engt typewwww rrwrrw ce h adc_qsr0 reset: 20 h queue status register 0 bit field rsv 0 empt y ev 0 fill type r r rh rh r rh cf h adc_q0r0 reset: 00 h queue 0 register 0 bit field extr ensi rf v 0 reqchnr type rh rh rh rh r rh d2 h adc_qbur0 reset: 00 h queue backup register 0 bit field extr ensi rf v 0 reqchnr type rh rh rh rh r rh d2 h adc_qinr0 reset: 00 h queue input register 0 bit field extr ensi rf 0 reqchnr typewww r w table 11 adc register overview (cont?d) addrregister name bit 76543210
xc87xclm functional description data sheet 47 v1.5, 2011-03 3.2.4.8 timer 2 compare/capture unit registers the timer 2 compare/capture unit sfrs can be accessed in the standard memory area (rmap = 0). table 12 t2ccu register overview addr register name bit 7 6 5 4 3 2 1 0 rmap = 0 c7 h t2_page reset: 00 h page register bit field op stnr 0 page type w w r rwh rmap = 0, page 0 c0 h t2_t2con reset: 00 h timer 2 control register bit field tf2 exf2 0 exen 2 tr2 c/t2 cp/ rl2 type rwh rwh r rw rwh rw rw c1 h t2_t2mod reset: 00 h timer 2 mode register bit field t2re gs t2rh en edge sel pren t2pre dcen type rw rw rw rw rw rw c2 h t2_rc2l reset: 00 h timer 2 reload/capture register low bit field rc2 type rwh c3 h t2_rc2h reset: 00 h timer 2 reload/capture register high bit field rc2 type rwh c4 h t2_t2l reset: 00 h timer 2 register low bit field thl2 type rwh c5 h t2_t2h reset: 00 h timer 2 register high bit field thl2 type rwh c6 h t2_t2con1 reset: 03 h timer 2 control register 1 bit field 0 tf2en exf2e n type r rw rw rmap = 0, page 1 c0 h t2ccu_ccen reset: 00 h t2ccu capture/compare enable register bit field ccm3 ccm2 ccm1 ccm0 type rw rw rw rw c1 h t2ccu_cctbselreset: 00 h t2ccu capture/compare time base select register bit field casc cctt ov cctb 5 cctb 4 cctb 3 cctb 2 cctb 1 cctb 0 type rwrwhrwrwrwrwrwrw c2 h t2ccu_cctrellreset: 00 h t2ccu capture/compare timer reload register low bit field cctrel type rw c3 h t2ccu_cctrelhreset: 00 h t2ccu capture/compare timer reload register high bit field cctrel type rw c4 h t2ccu_cctl reset: 00 h t2ccu capture/compare timer register low bit field cct type rwh
xc87xclm functional description data sheet 48 v1.5, 2011-03 c5 h t2ccu_ccth reset: 00 h t2ccu capture/compare timer register high bit field cct type rwh c6 h t2ccu_cctcon reset: 00 h t2ccu captureccompare timer control register bit field cctpre ccto vf ccto ven timsy n ccts t type rw rwh rw rw rw rmap = 0, page 2 c0 h t2ccu_coshdwreset: 00 h t2ccu capture/compare enable register bit field ensh dw txov coou t5 coou t4 coou t3 coou t2 coou t1 coou t0 type rwh rwh rwh rwh rwh rwh rwh rwh c1 h t2ccu_cc0l reset: 00 h t2ccu capture/compare register 0 low bit field ccvall type rwh c2 h t2ccu_cc0h reset: 00 h t2ccu capture/compare register 0 high bit field ccvalh type rwh c3 h t2ccu_cc1l reset: 00 h t2ccu capture/compare register 1 low bit field ccvall type rwh c4 h t2ccu_cc1h reset: 00 h t2ccu capture/compare register 1 high bit field ccvalh type rwh c5 h t2ccu_cc2l reset: 00 h t2ccu capture/compare register 2 low bit field ccvall type rwh c6 h t2ccu_cc2h reset: 00 h t2ccu capture/compare register 2 high bit field ccvalh type rwh rmap = 0, page 3 c0 h t2ccu_cocon reset: 00 h t2ccu compare control register bit field ccm5 ccm4 cm5f cm4f polb pola comod type rw rw rwh rwh rw rw rw c1 h t2ccu_cc3l reset: 00 h t2ccu capture/compare register 3 low bit field ccvall type rwh c2 h t2ccu_cc3h reset: 00 h t2ccu capture/compare register 3 high bit field ccvalh type rwh c3 h t2ccu_cc4l reset: 00 h t2ccu capture/compare register 4 low bit field ccvall type rwh c4 h t2ccu_cc4h reset: 00 h t2ccu capture/compare register 4 high bit field ccvalh type rwh c5 h t2ccu_cc5l reset: 00 h t2ccu capture/compare register 5 low bit field ccvall type rwh c6 h t2ccu_cc5h reset: 00 h t2ccu capture/compare register 5 high bit field ccvalh type rwh table 12 t2ccu register overview (cont?d) addr register name bit 7 6 5 4 3 2 1 0
xc87xclm functional description data sheet 49 v1.5, 2011-03 3.2.4.9 timer 21 registers the timer 21 sfrs can be accessed in the mapped memory area (rmap = 1). rmap = 0, page 4 c2 h t2ccu_cctdtclreset: 00 h t2ccu capture/compare timer dead-time control register low bit field dtm type rw c3 h t2ccu_cctdtchreset: 00 h t2ccu capture/compare timer dead-time control register high bit field dtre s dtr2 dtr1 dtr0 dtlev dte2 dte1 dte0 type rwhrh rh rhrwrwrwrw table 13 t21 register overview addr register name bit 7 6 5 4 3 2 1 0 rmap = 1 c0 h t21_t2con reset: 00 h timer 2 control register bit field tf2 exf2 0 exen 2 tr2 c/t2 cp/ rl2 type rwh rwh r rw rwh rw rw c1 h t21_t2mod reset: 00 h timer 2 mode register bit field t2re gs t2rh en edge sel pren t2pre dcen type rw rw rw rw rw rw rw rw c2 h t21_rc2l reset: 00 h timer 2 reload/capture register low bit field rc2 type rwh c3 h t21_rc2h reset: 00 h timer 2 reload/capture register high bit field rc2 type rwh c4 h t21_t2l reset: 00 h timer 2 register low bit field thl2 type rwh c5 h t21_t2h reset: 00 h timer 2 register high bit field thl2 type rwh c6 h t21_t2con1 reset: 03 h timer 2 control register 1 bit field 0 tf2en exf2e n type r rw rw table 12 t2ccu register overview (cont?d) addr register name bit 7 6 5 4 3 2 1 0
xc87xclm functional description data sheet 50 v1.5, 2011-03 3.2.4.10 ccu6 registers the ccu6 sfrs can be accessed in the standard memory area (rmap = 0). table 14 ccu6 register overview addrregister name bit 76543210 rmap = 0 a3 h ccu6_page reset: 00 h page register bit field op stnr 0 page type w w r rwh rmap = 0, page 0 9a h ccu6_cc63srl reset: 00 h capture/compare shadow register for channel cc63 low bit field cc63sl type rw 9b h ccu6_cc63srh reset: 00 h capture/compare shadow register for channel cc63 high bit field cc63sh type rw 9c h ccu6_tctr4l reset: 00 h timer control register 4 low bit field t12 std t12 str 0 dt res t12 res t12r s t12r r type ww r wwww 9d h ccu6_tctr4h reset: 00 h timer control r egister 4 high bit field t13 std t13 str 0 t13 res t13r s t13r r type ww r www 9e h ccu6_mcmoutsl reset: 00 h multi-channel mode output shadow register low bit field strm cm 0 mcmps type w r rw 9f h ccu6_mcmoutsh reset: 00 h multi-channel mode output shadow register high bit field strh p 0 curhs exphs type w r rw rw a4 h ccu6_isrl reset: 00 h capture/compare interrupt status reset register low bit field rt12 pm rt12 om rcc6 2f rcc6 2r rcc6 1f rcc6 1r rcc6 0f rcc6 0r type wwwwwwww a5 h ccu6_isrh reset: 00 h capture/compare interrupt status reset register high bit field rstr ridle rwh e rche 0 rtrp f rt13 pm rt13 cm type wwww r www a6 h ccu6_cmpmodifl reset: 00 h compare state modification register low bit field 0 mcc6 3s 0 mcc6 2s mcc6 1s mcc6 0s type r w r www a7 h ccu6_cmpmodifh reset: 00 h compare state modification register high bit field 0 mcc6 3r 0 mcc6 2r mcc6 1r mcc6 0r type r w r www fa h ccu6_cc60srl reset: 00 h capture/compare shadow register for channel cc60 low bit field cc60sl type rwh fb h ccu6_cc60srh reset: 00 h capture/compare shadow register for channel cc60 high bit field cc60sh type rwh
xc87xclm functional description data sheet 51 v1.5, 2011-03 fc h ccu6_cc61srl reset: 00 h capture/compare shadow register for channel cc61 low bit field cc61sl type rwh fd h ccu6_cc61srh reset: 00 h capture/compare shadow register for channel cc61 high bit field cc61sh type rwh fe h ccu6_cc62srl reset: 00 h capture/compare shadow register for channel cc62 low bit field cc62sl type rwh ff h ccu6_cc62srh reset: 00 h capture/compare shadow register for channel cc62 high bit field cc62sh type rwh rmap = 0, page 1 9a h ccu6_cc63rl reset: 00 h capture/compare register for channel cc63 low bit field cc63vl type rh 9b h ccu6_cc63rh reset: 00 h capture/compare register for channel cc63 high bit field cc63vh type rh 9c h ccu6_t12prl reset: 00 h timer t12 period register low bit field t12pvl type rwh 9d h ccu6_t12prh reset: 00 h timer t12 period register high bit field t12pvh type rwh 9e h ccu6_t13prl reset: 00 h timer t13 period register low bit field t13pvl type rwh 9f h ccu6_t13prh reset: 00 h timer t13 period register high bit field t13pvh type rwh a4 h ccu6_t12dtcl reset: 00 h dead-time control register for timer t12 low bit field dtm type rw a5 h ccu6_t12dtch reset: 00 h dead-time control register for timer t12 high bit field 0 dtr2 dtr1 dtr0 0 dte2 dte1 dte0 type r rhrhrh r rwrwrw a6 h ccu6_tctr0l reset: 00 h timer control register 0 low bit field ctm cdir ste1 2 t12r t12 pre t12clk type rw rh rh rh rw rw a7 h ccu6_tctr0h reset: 00 h timer control r egister 0 high bit field 0 ste1 3 t13r t13 pre t13clk type r rh rh rw rw fa h ccu6_cc60rl reset: 00 h capture/compare register for channel cc60 low bit field cc60vl type rh fb h ccu6_cc60rh reset: 00 h capture/compare register for channel cc60 high bit field cc60vh type rh fc h ccu6_cc61rl reset: 00 h capture/compare register for channel cc61 low bit field cc61vl type rh table 14 ccu6 register overview (cont?d) addrregister name bit 76543210
xc87xclm functional description data sheet 52 v1.5, 2011-03 fd h ccu6_cc61rh reset: 00 h capture/compare register for channel cc61 high bit field cc61vh type rh fe h ccu6_cc62rl reset: 00 h capture/compare register for channel cc62 low bit field cc62vl type rh ff h ccu6_cc62rh reset: 00 h capture/compare register for channel cc62 high bit field cc62vh type rh rmap = 0, page 2 9a h ccu6_t12msell reset: 00 h t12 capture/compare mode select register low bit field msel61 msel60 type rw rw 9b h ccu6_t12mselh reset: 00 h t12 capture/compare mode select register high bit field dbyp hsync msel62 type rw rw rw 9c h ccu6_ienl reset: 00 h capture/compare interrupt enable register low bit field ent1 2 pm ent1 2 om encc 62f encc 62r encc 61f encc 61r encc 60f encc 60r type rw rw rw rw rw rw rw rw 9d h ccu6_ienh reset: 00 h capture/compare interrupt enable register high bit field en str en idle en whe en che 0 en trpf ent1 3pm ent1 3cm type rw rw rw rw r rw rw rw 9e h ccu6_inpl reset: 40 h capture/compare interrupt node pointer register low bit field inpche inpcc62 inpcc61 inpcc60 type rw rw rw rw 9f h ccu6_inph reset: 39 h capture/compare interrupt node pointer register high bit field 0 inpt13 inpt12 inperr type r rw rw rw a4 h ccu6_issl reset: 00 h capture/compare interrupt status set register low bit field st12 pm st12 om scc6 2f scc6 2r scc6 1f scc6 1r scc6 0f scc6 0r type wwwwwwww a5 h ccu6_issh reset: 00 h capture/compare interrupt status set register high bit field sstr sidle swhe sche swh c strp f st13 pm st13 cm type wwwwwwww a6 h ccu6_pslr reset: 00 h passive state level register bit field psl63 0 psl type rwh r rwh a7 h ccu6_mcmctr reset: 00 h multi-channel mode control register bit field 0 swsyn 0 swsel type r rw r rw fa h ccu6_tctr2l reset: 00 h timer control register 2 low bit field 0 t13ted t13tec t13 ssc t12 ssc type r rw rw rw rw fb h ccu6_tctr2h reset: 00 h timer control r egister 2 high bit field 0 t13rsel t12rsel type r rw rw fc h ccu6_modctrl reset: 00 h modulation contro l register low bit field mcm en 0 t12moden type rw r rw table 14 ccu6 register overview (cont?d) addrregister name bit 76543210
xc87xclm functional description data sheet 53 v1.5, 2011-03 fd h ccu6_modctrh reset: 00 h modulation contro l register high bit field ect1 3o 0 t13moden type rw r rw fe h ccu6_trpctrl reset: 00 h trap control register low bit field 0 trpm 2 trpm 1 trpm 0 type r rw rw rw ff h ccu6_trpctrh reset: 00 h trap control register high bit field trpp en trpe n13 trpen type rw rw rw rmap = 0, page 3 9a h ccu6_mcmoutl reset: 00 h multi-channel mode output register low bit field 0 r mcmp type r rh rh 9b h ccu6_mcmouth reset: 00 h multi-channel mode output register high bit field 0 curh exph type r rh rh 9c h ccu6_isl reset: 00 h capture/compare interrupt status register low bit field t12 pm t12 om icc62 f icc62 r icc61 f icc61 r icc60 f icc60 r type rh rh rh rh rh rh rh rh 9d h ccu6_ish reset: 00 h capture/compare interrupt status register high bit field str idle whe che trps trpf t13 pm t13 cm type rh rh rh rh rh rh rh rh 9e h ccu6_pisel0l reset: 00 h port input select register 0 low bit field istrp iscc62 iscc61 iscc60 type rw rw rw rw 9f h ccu6_pisel0h reset: 00 h port input select register 0 high bit field ist12hr ispos2 ispos1 ispos0 type rw rw rw rw a4 h ccu6_pisel2 reset: 00 h port input select register 2 bit field 0 ist13hr type r rw fa h ccu6_t12l reset: 00 h timer t12 counter register low bit field t12cvl type rwh fb h ccu6_t12h reset: 00 h timer t12 counter register high bit field t12cvh type rwh fc h ccu6_t13l reset: 00 h timer t13 counter register low bit field t13cvl type rwh fd h ccu6_t13h reset: 00 h timer t13 counter register high bit field t13cvh type rwh fe h ccu6_cmpstatl reset: 00 h compare state register low bit field 0 cc63 st cc pos2 cc pos1 cc pos0 cc62 st cc61 st cc60 st type r rhrhrhrhrhrhrh ff h ccu6_cmpstath reset: 00 h compare state register high bit field t13im cout 63ps cout 62ps cc62 ps cout 61ps cc61 ps cout 60ps cc60 ps type rwh rwh rwh rwh rwh rwh rwh rwh table 14 ccu6 register overview (cont?d) addrregister name bit 76543210
xc87xclm functional description data sheet 54 v1.5, 2011-03 3.2.4.11 uart1 registers the uart1 sfrs can be accessed in the mapped memory area (rmap = 1). 3.2.4.12 ssc registers the ssc sfrs can be accessed in the standard memory area (rmap = 0). table 15 uart1 register overview addr register name bit 7 6 5 4 3 2 1 0 rmap = 1 c8 h scon reset: 00 h serial channel control register bit field sm0 sm1 sm2 ren tb8 rb8 ti ri type rw rw rw rw rw rwh rwh rwh c9 h sbuf reset: 00 h serial data buffer register bit field val type rwh ca h bcon reset: 00 h baud rate control register bit field 0 brpre r type r rw rw cb h bg reset: 00 h baud rate timer/reload register bit field br_value type rwh cc h fdcon reset: 00 h fractional divider control register bit field 0 ndov fdm fden type r rwh rw rw cd h fdstep reset: 00 h fractional divider reload register bit field step type rw ce h fdres reset: 00 h fractional divider result register bit field result type rh cf h scon1 reset: 07 h serial channel control register 1 bit field 0 ndov en tien rien type r rw rw rw table 16 ssc register overview addr register name bit 7 6 5 4 3 2 1 0 rmap = 0 a9 h ssc_pisel reset: 00 h port input select register bit field 0 cis sis mis type r rw rw rw aa h ssc_conl reset: 00 h control register low programming mode bit field lb po ph hb bm type rw rw rw rw rw aa h ssc_conl reset: 00 h control register low operating mode bit field 0 bc type r rh ab h ssc_conh reset: 00 h control register high programming mode bit field en ms 0 aren ben pen ren ten type rw rw r rw rw rw rw rw
xc87xclm functional description data sheet 55 v1.5, 2011-03 3.2.4.13 multican registers the multican sfrs can be accessed in the standard memory area (rmap = 0). 3.2.4.14 ocds registers the ocds sfrs can be accessed in the mapped memory area (rmap = 1). ab h ssc_conh reset: 00 h control register high operating mode bit field en ms 0 bsy be pe re te type rw rw r rh rwh rwh rwh rwh ac h ssc_tbl reset: 00 h transmitter buffer register low bit field tb_value type rw ad h ssc_rbl reset: 00 h receiver buffer register low bit field rb_value type rh ae h ssc_brl reset: 00 h baud rate timer reload register low bit field br_value type rw af h ssc_brh reset: 00 h baud rate timer reload register high bit field br_value type rw table 17 can register overview addr register name bit 7 6 5 4 3 2 1 0 rmap = 0 d8 h adcon reset: 00 h can address/da ta control register bit field v3 v2 v1 v0 auad bsy rwen type rw rw rw rw rw rh rw d9 h adl reset: 00 h can address register low bit field ca9 ca8 ca7 ca6 ca5 ca4 ca3 ca2 type rwh rwh rwh rwh rwh rwh rwh rwh da h adh reset: 00 h can address register high bit field 0 ca13 ca12 ca11 ca10 type r rwh rwh rwh rwh db h data0 reset: 00 h can data register 0 bit field cd type rwh dc h data1 reset: 00 h can data register 1 bit field cd type rwh dd h data2 reset: 00 h can data register 2 bit field cd type rwh de h data3 reset: 00 h can data register 3 bit field cd type rwh table 16 ssc register overview (cont?d) addr register name bit 7 6 5 4 3 2 1 0
xc87xclm functional description data sheet 56 v1.5, 2011-03 table 18 ocds register overview addr register name bit 7 6 5 4 3 2 1 0 rmap = 1 e9 h mmcr2 reset: 8u h monitor mode control 2 register bit field stmo de exbc dsus p mbco n altdi mmep mmod e jena type rw rw rw rwh rw rwh rh rh ea h mextcr reset: 0u h memory extension control register bit field 0 bankbpx type r rw eb h mmwr1 reset: 00 h monitor work register 1 bit field mmwr1 type rw ec h mmwr2 reset: 00 h monitor work register 2 bit field mmwr2 type rw f1 h mmcr reset: 00 h monitor mode control register bit field mexit _p mexit 0 mste p mram s_p mram s trf rrf type w rwh r rw w rwh rh rh f2 h mmsr reset: 00 h monitor mode status register bit field mbca m mbcin exbf swbf hwb3 f hwb2 f hwb1 f hwb0 f type rw rwh rwh rwh rwh rwh rwh rwh f3 h mmbpcr reset: 00 h breakpoints control register bit field swbc hwb3c hwb2c hwb1 c hwb0c type rw rw rw rw rw f4 h mmicr reset: 00 h monitor mode interrupt control register bit field dvec t dret r comr st msts el mmui e_p mmui e rrie_ p rrie type rwh rwh rwh rh w rw w rw f5 h mmdr reset: 00 h monitor mode data transfer register receive bit field mmrr type rh f6 h hwbpsr reset: 00 h hardware breakpoints select register bit field 0 bpsel _p bpsel type r w rw f7 h hwbpdr reset: 00 h hardware breakpoints data register bit field hwbpxx type rw
xc87xclm functional description data sheet 57 v1.5, 2011-03 3.2.4.15 flash registers the flash sfrs can be accessed in the mapped memory area (rmap = 1). table 19 flash register overview addr register name bit 7 6 5 4 3 2 1 0 rmap = 1 d1 h fcon reset: 10 h p-flash control register bit field 0 fbsy ye 1 nvst r mas1 eras e prog type r rh rwh r rw rw rw rw d2 h eecon reset: 10 h d-flash control register bit field 0 eebs y ye 1 nvst r mas1 eras e prog type r rh rwh r rw rw rw rw d3 h fcs reset: 80 h flash control and status register bit field 1 sbeie ften 0 eede rr eese rr fder r fser r type r rw rwh r rwh rwh rwh rwh d4 h feal reset: 00 h flash error address register, low byte bit field ecceaddr type rh d5 h feah reset: 00 h flash error address register, high byte bit field ecceaddr type rh d6 h ftval reset: 78 h flash timer value register bit field mode ofval type rw rw dd h fcs1 reset: 00 h flash control and status register 1 bit field 0 eeab ort type r rwh
xc87xclm functional description data sheet 58 v1.5, 2011-03 3.3 flash memory the flash memory provides an embedded user-programm able non-volatile memory, allowing fast and reliable storage of user code and data. it is operated from a single 2.5 v supply from the embedded voltage regu lator (evr) and does not require additional programming or erasing voltage. the paginat ion of the flash me mory allows each page to be erased independently. features ? in-system programming (isp) via uart ? in-application programming (iap) ? error correction code (ecc) for dynamic correction of single-bit errors ? background program a nd erase operations for cpu load minimization ? support for aborti ng erase operation ? minimum program width ? of 1-byte for d-flash and 2-bytes for p-flash ? 1-page minimum erase width ? 1-byte read access ? flash is deliver ed in erased stat e (read all ones) ? operating supply vo ltage: 2.5 v 7.5 % ? read access time: 1 t cclk =38 ns 1) ? program time for 1 wordline: 1.6 ms 2) ? page erase time: 20 ms ? mass erase time: 200 ms 1) values shown here are typical values. f sys = 144 mhz 7.5% ( f cclk = 24 mhz 7.5 %) is the maximum frequency range for flash read access. 2) values shown here are typical values. f sys = 144 mhz 7.5% ( f cclk = 24 mhz 7.5 %) is the typical frequency range for flash programming and erasing. f sysmin is used for obtaining the worst case timing.
xc87xclm functional description data sheet 59 v1.5, 2011-03 table 20 and table 21 shows the flash data retent ion and endurance targets for industrial profile and automo tive profile respectively. table 20 flash data retention and endurance for industrial profile (operating conditions apply) retention endurance 1)2) 1) in program flash, one cycle refers to the programming of all pages in the flash bank and a mass erase. 2) in data flash, one cycle refers to the programming of all wordlines in a page and a page erase. size remarks program flash 15 years 1000 cycles up to 60 kbytes data flash 15 years 1000 cycles 4 kbytes 10 years 10,000 cycles 4 kbytes 5 years 30,000 cycles 4 kbytes 1 year 100,000 cycles 4 kbytes saf and sax variant 80,000 cycles sak variant table 21 flash data retention an d endurance for automotive profile (operating conditions apply) retention endurance 1)2) 1) in program flash, one cycle refers to the programming of all pages in the flash bank and a mass erase. 2) in data flash, one cycle refers to the programming of all wordlines in a page and a page erase. size remarks program flash 15 years 1000 cycles up to 60 kbytes data flash 15 years 1000 cycles 4 kbytes 5 years 10,000 cycles 1 kbytes 2 years 15,000 cycles 512 bytes 2 years 30,000 cycles 256 bytes 1 year 100,000 cycles 128 bytes
xc87xclm functional description data sheet 60 v1.5, 2011-03 3.3.1 flash bank pagination the xc87x product family offe rs flash devices with either 64 kbytes or 52 kbytes of embedded flash memory. each flash device co nsists of a program flash (p-flash) and a single data flash (d-flash) bank. p-flash has 120 pages of 8 wordlines per page with 64 bytes per wordline. d-flash has 64 pages of 2 wordlines per page with 32 bytes per wordline. both types can be used for code and data storage.. th e label ?data? neither implies that the d-flash is mapped to the data memory re gion, nor that it can only be used for data storage. it is used to dist inguish the different p age width and wordline of each flash bank. the internal structure of eac h flash bank represents a page architecture for flexible erase capability. the minimu m erase width is always a co mplete page. the d-flash bank is divided into smaller size for extended erasing and repr ogramming capability; even numbers for each page size are provided to allow greater flexibility and the ability to adapt to a wide range of application requirements.
xc87xclm functional description data sheet 61 v1.5, 2011-03 3.4 interrupt system the xc800 core supports one non-maskable interrupt (nmi ) and 14 maskable interrupt requests. in addition to the standard interr upt functions supporte d by the core, e.g., configurable interrup t priority and interrupt maski ng, the xc87x interrupt system provides extended interrupt su pport capabilitie s such as the mapping of each interrupt vector to several interrupt sources to increase the number of interrupt sources supported, and additional stat us registers for detecting and determining the interrupt source. 3.4.1 interrupt source figure 12 to figure 16 give a general overview of t he interrupt sour ces and nodes, and their corresponding co ntrol and status flags. figure 12 non-maskable in terrupt request sources 0073 h nmiwdt nmicon.0 wdt overflow >=1 non maskable interrupt nmipll nmicon.1 pll loss of clock nmiflash flash timer overflow fnmiwdt nmiisr.0 fnmipll nmiisr.1 fnmiflash nmiisr.2 nmivddp nmicon.5 vddp pre-warning fnmivddp nmiisr.5 nmiecc nmicon.6 flash ecc error fnmiecc nmiisr.6 nmicon.2
xc87xclm functional description data sheet 62 v1.5, 2011-03 figure 13 interrupt request sources (part 1) highest lowest priority leve l bit-addressable request flag is cleared by hardware 000b h et0 ien0.1 tf0 tcon.5 timer 0 overflow 001b h et1 ien0.3 tf1 tcon.7 timer 1 overflow ip.1/ iph.1 ip.3/ iph.3 0023 h es ien0.4 ip.4/ iph.4 >=1 ri scon.0 ti scon.1 uart transmit 0003 h ex0 ien0.0 ie0 tcon.1 ip.0/ iph.0 0013 h ip.2/ iph.2 it0 tcon.0 ex1 ien0.2 ie1 tcon.3 it1 tcon.2 ien0.7 ea p o l l i n g s e q u e n c e uart receive exint0 exicon0.0/1 eint0 exint1 exicon0.2/3 eint1
xc87xclm functional description data sheet 63 v1.5, 2011-03 figure 14 interrupt request sources (part 2) highest lowest priority level bit- addressable request flag is cleared by hardware 002b h ip.5/ iph.5 p o l l i n g s e q u e n c e 0033 h eadc ien1.0 ip1.0/ iph1.0 >=1 adcsrc0 ircon1.3 adcsrc1 ircon1.4 cansrc1 ircon1.5 et2 ien0.5 >=1 tf2 t2_t2con.7 exf2 t2_t2con.6 timer 2 overflow exen2 t2_t2con.3 cansrc0 ircon2.0 ndov fdcon.2 normal divider overflow synen fdcon.6 eofsyn fdcon.4 end of syn byte errsyn fdcon.5 syn byte error ien0.7 ea cansrc2 ircon1.6 t2ex edges el t2_t2mod.5 >=1 exf2en t2_t2con1.0 tf2en t2_t2con1.1 cctovf t2ccu_cctcon.3 cct overflow cctoven t2ccu_cctcon.2 ndoven bcon.5 multican node 0 adc service request 0 adc service request 1 multican node 1 multican node 2
xc87xclm functional description data sheet 64 v1.5, 2011-03 figure 15 interrupt request sources (part 3) highest lowest priority level bit- addressable request flag is cleared by hardware p o l l i n g s e q u e n c e 003b h essc ien1.1 ip1.1/ iph1.1 >=1 tir ircon1.1 rir ircon1.2 eir ircon1.0 ien0.7 ea 0043 h ip1.2/ iph1.2 exint2 exicon0.4/5 exint2 ircon0.2 eint2 ex2 ien1.2 irdy mdustat.0 ierr mdustat.1 eoc cdstatc.2 cordic >=1 >=1 ri uart1_scon.0 ti uart1_scon.1 uart1 ndov uart1 normal divider overflow uart1_fdcon.2 eiren modien.0 tiren modien.1 riren modien.2 ndoven uart1_scon1.2 tf2 t21_t2con.7 exf2 t21_t2con.6 timer 21 overflow exen2 t21_t2con.3 t21ex edges el t21_t2mod.5 >=1 exf2en t21_t2con1.0 tf2en t21_t2con1.1 rien uart1_scon1.0 tien uart1_scon1.1 ssc error ssc transmit ssc receive mdu result ready mdu error
xc87xclm functional description data sheet 65 v1.5, 2011-03 figure 16 interrupt request sources (part 4) ien0.7 highest lowest priority level bit- addressable request flag is cleared by hardware p o l l i n g s e q u e n c e ea 004b h exm ien1.3 ip1.3/ iph1.3 >=1 exint5 exicon1.2/3 exint5 ircon0.5 t2cc2/ eint5 exint4 exicon1.0/1 exint4 ircon0.4 t2cc1/ eint4 exint3 exicon0.6/7 exint3 ircon0.3 t2cc0/ eint3 exint6 exicon1.4/5 exint6 ircon0.6 t2cc3/ eint6 cansrc3 ircon2.4 multican node 3 cm4f t2ccu_cocon.4 compare channel 4 cm4en modien.3 cm5f t2ccu_cocon.5 compare channel 5 cm5en modien.4
xc87xclm functional description data sheet 66 v1.5, 2011-03 figure 17 interrupt request sources (part 5) highest lowest priority level p o l l i n g s e q u e n c e ien0.7 bit-addressable request flag is cleared by hardware ea 0053 h ccu6 interrupt node 0 ip1.4/ iph1.4 005b h ip1.5/ iph1.5 0063 h ip1.6/ iph1.6 006b h ip1.7/ iph1.7 eccip0 ien1.4 eccip1 ien1.5 eccip2 ien1.6 eccip3 ien1.7 cansrc4 ircon3.1 multican node 4 >=1 ccu6 interrupt node 1 cansrc5 ircon3.5 multican node 5 >=1 ccu6 interrupt node 2 cansrc6 ircon4.1 multican node 6 >=1 ccu6 interrupt node 3 cansrc7 ircon4.5 multican node 7 >=1 ccu6sr0 ircon3.0 ccu6sr1 ircon3.4 ccu6sr2 ircon4.0 ccu6src3 ircon4.4
xc87xclm functional description data sheet 67 v1.5, 2011-03 3.4.2 interrupt source and vector each interrupt event source has an associat ed interrupt vector addr ess for the interrupt node it belongs to. this vect or is accessed to service th e corresponding interrupt node request. the interrupt service of each inte rrupt source can be in dividually enabled or disabled via an enable bit. the assignment of the xc87x interrupt sources to the interrupt vector a ddress and the corresponding inte rrupt node enable bits are summarized in table 22 . table 22 interrupt vector addresses interrupt source vector address assignment for xc87x enable bit sfr nmi 0073 h watchdog timer nmi nmiwdt nmicon pll nmi nmipll flash timer nmi nmiflash v ddp prewarning nmi nmivddp flash ecc nmi nmiecc xintr0 0003 h external interrupt 0 ex0 ien0 xintr1 000b h timer 0 et0 xintr2 0013 h external interrupt 1 ex1 xintr3 001b h timer 1 et1 xintr4 0023 h uart es xintr5 002b h t2ccu et2 uart fractional divider (normal divider overflow) multican node 0 lin
xc87xclm functional description data sheet 68 v1.5, 2011-03 xintr6 0033 h multican nodes 1 and 2 eadc ien1 adc[1:0] xintr7 003b h ssc essc xintr8 0043 h external interrupt 2 ex2 t21 cordic uart1 uart1 fractional divider (normal divider overflow) mdu[1:0] xintr9 004b h external interrupt 3 exm external interrupt 4 external interrupt 5 external interrupt 6 t2ccu multican node 3 xintr10 0053 h ccu6 inp0 eccip0 multican node 4 xintr11 005b h ccu6 inp1 eccip1 multican node 5 xintr12 0063 h ccu6 inp2 eccip2 multican node 6 xintr13 006b h ccu6 inp3 eccip3 multican node 7 table 22 interrupt vector addresses (cont?d) interrupt source vector address assignment for xc87x enable bit sfr
xc87xclm functional description data sheet 69 v1.5, 2011-03 3.4.3 interrupt priority an interrupt that is currentl y being serviced can only be in terrupted by a higher-priority interrupt, but not by ano ther interrupt of the sa me or lower priority. hence, an interrupt of the highest priority cannot be interr upted by any other interrupt request. if two or more requests of different priority levels ar e received simultaneously, the request of the highest priority is serviced first. if requests of th e same prio rity are received simultaneously, then an internal pol ling sequence determi nes which request is serviced first. thus, within ea ch priority level, there is a second priority structure determined by the polli ng sequence shown in table 23 . table 23 priority structur e within interrupt level source level non-maskable interrupt (nmi) (highest) external interrupt 0 1 timer 0 interrupt 2 external interrupt 1 3 timer 1 interrupt 4 uart interrupt 5 t2ccu,uart normal divider overflow, multican, lin interrupt 6 adc, multican interrupt 7 ssc interrupt 8 external interrupt 2, timer 21, ua rt1, uart1 normal divider overflow, mdu, cordic interrupt 9 external interrupt [6:3 ], multican interrupt 10 ccu6 interrupt node pointe r 0, multican interrupt 11 ccu6 interrupt node pointe r 1, multican interrupt 12 ccu6 interrupt node pointe r 2, multican interrupt 13 ccu6 interrupt node pointe r 3, multican interrupt 14
xc87xclm functional description data sheet 70 v1.5, 2011-03 3.5 parallel ports the xc87x has 40 port pins orga nized into five parallel ports: port 0 (p0), port 1 (p1), port 3 (p3), port 4 (p4) and port 5 (p5). each pin has a pai r of internal pull-up and pull- down devices that can be individually enabl ed or disabled. these ports are bidirectional and can be used as g eneral purpose input/ output (gpio) or to perform alternate input/output functions for the on-chip peripherals. when co nfigured as an output, the open drain mode can be selected. bidirectional port features ? configurable pin direction ? configurable pull-up /pull-down devices ? configurable open drain mode ? configurable drive strength ? transfer of data through digital inpu ts and outputs (ge neral purpose i/o) ? alternate input/output for on-chip peripherals
xc87xclm functional description data sheet 71 v1.5, 2011-03 figure 18 shows the structure of a bidirectional port pin. figure 18 general structur e of bidirectional port px_od open drain control register px_data data register internal bus alt dat aout 3 alt dat aout 2 px_altsel0 alternate select register 0 px_altsel1 alternate select register 1 alt dat ai n pin px_ds drive strength control register px_di r direction register px_puden pull-up/pull-down enable register alt dat aout 1 pad out in pull device output driver i nput driver 11 10 01 00 schmit t trigger opendrain/output control logic 1 0 px _ pudsel pull-up/pull-down select register pull-up/pull-down control logic
xc87xclm functional description data sheet 72 v1.5, 2011-03 3.6 power supply system with embedded voltage regulator the xc87x microcontroller requires tw o different levels of power supply: ? 3.3 v or 5.0 v for the embedded vo ltage regulator (evr) and ports ? 2.5 v for the core, memory, on-ch ip oscillator, and peripherals figure 19 shows the xc87x power supply system. a power supply of 3.3 v or 5.0 v must be provided from the external power supply pin. the 2.5 v power supply for the logic is generated by the evr. the evr help s to reduce the power consumption of the whole chip and the co mplexity of the app lication board design. the evr consists of a main voltage regula tor and a low power voltage regulator. in active mode, both voltage regulato rs are enabled. in power-down mode 1) , the main voltage regulator is switched off, while the low power voltage re gulator continues to function and provide power supply to th e system with low power consumption. figure 19 xc87x power supply system evr features ? input voltage ( v ddp ): 3.3 v/5.0 v ? output voltage ( v ddc ): 2.5 v 7.5% ? low power voltage regulator provided in power-down mode 1) ? v ddp prewarning detection ? v ddc brownout detection 1) sak product variant does not support power-down mode. on-chip osc cpu & memory v ddc (2.5v) v ddp (3.3v/5.0v) v ssp gpio ports (p0-p5) evr peripheral logic flash adc pll xtal1& xtal2
xc87xclm functional description data sheet 73 v1.5, 2011-03 3.7 reset control the xc87x has five types of reset: power- on reset, hardware re set, watchdog timer reset, power-down wake-up re set, and brownout reset. when the xc87x is first powered up, t he status of cert ain pins (see table 25 ) must be defined to ensure proper star t operation of the device. at the end of a reset sequence, the sampled values are latched to select the desired b oot option, which cannot be modified until the next power-on reset or hardware reset. th is guarantees stable conditions during the norma l operation of the device. the second type of reset in xc87x is the hardware reset. this reset function can be used during normal operation or when the chip is in power-down mode . a reset input pin reset is provided for the hardware reset. the watchdog timer (wdt) module is also capable of resett ing the device if it detects a malfunction in the system. another type of reset that needs to be detected is a re set while the device is in power-down mode (wake-up reset). while the contents of the stat ic ram are undefined after a power-on reset, they are well defin ed after a wake-up reset from power-down mode. 3.7.1 module reset behavior table 24 lists the functions of th e xc87x and the various rese t types that affect these functions. the symbol ? ? signifies that the particular func tion is reset to its default state. table 24 effect of reset on device functions module/ function wake-up reset watchdog reset hardware reset power-on reset brownout reset cpu core peripherals on-chip static ram not affected, reliable not affected, reliable not affected, reliable affected, un- reliable affected, un- reliable oscillator, pll not affected port pins evr the voltage regulator is switched on not affected not affected flash nmi disabled disabled
xc87xclm functional description data sheet 74 v1.5, 2011-03 3.7.2 booting scheme when the xc87x is reset, it mu st identify the type of confi guration with which to start the different modes once the re set sequence is complete. thus, boot configuration information that is required for activation of special modes and condit ions needs to be applied by the external world through input pins. after power-on reset or hardware reset, the pins mbc, tms and p0 .0 collectively select t he different boot options. table 25 shows the available boot options in the xc87x. note: the boot options are valid only with t he default set of uart and jtag pins. table 25 xc87x boot selection 1) 1) in addition to the pins mbc, tms and p0.0, tm pin also requires an external pull down for all the boot options. mbc tms p0.0 type of mode pc start value 1 0 x user mode 2) ; on-chip osc/pll non-bypassed 2) bsl mode is automatically entered if no valid password is installed and data at memory address 0000h equals zero. 0000 h 0 0 x bsl mode; (lin mode 3) , uart/ multican mode 4)5) and alternate bsl mode 6) ); on-chip osc/pll non-bypassed 3) if a device is programmed as lin, lin bsl is always used instead of uart/multican. 4) uart or multican bsl is decoded by firmware based on th e protocol for product vari ant with multican. if no multican and lin variant, uart bsl is used. 5) in multican bsl mode, the clock source is switched to xtal by firmware, bypassing the on-chip oscillator. this avoids any frequency invariance with the on-chip oscillator and allows other frequency clock input, thus ensuring accurate baud rate detection (especially at high bit rates). 6) alternate bsl mode is a user defined bsl code programmed in flash. it is entered if the altbslpassword is valid. 0000 h 0 1 0 ocds mode; on-chip osc/pll non- bypassed 0000 h 1 1 0 user (jtag) mode 7) ; on-chip osc/pll non- bypassed (normal) 7) normal user mode with standard jtag (t ck,tdi,tdo) pins for hot-attach purpose. 0000 h
xc87xclm functional description data sheet 75 v1.5, 2011-03 3.8 clock generation unit the clock generation unit (cgu ) allows great flexibility in the clock generation for the xc87x. the power consumption is indirectly proportional to the frequency, whereas the performance of the microcontroller is direct ly proportional to th e frequency. during user program execution, the fr equency can be programmed fo r an optimal ratio between performance and power cons umption. therefore the power consumption can be adapted to the actual application state. features ? phase-locked loop (pll) for multiplyin g clock source by different factors ?pll base mode ? prescaler mode ?pll mode ? power-down mode support 1) the cgu consists of an oscilla tor circuit and a pl l. in the xc87x, t he oscillator can be from either of these two sour ces: the on-chip oscillator (4 mh z) or the external oscillator (2 mhz to 20 mhz). the term ?oscillator? is used to refer to both on-chip oscillator and external oscillator, unless ot herwise stated. after the reset, the on-chip oscillator will be used by default.the external o scillator can be selected via so ftware. in addition, the pll provides a fail-safe logic to perform oscillator run and loss-of -lock detection. this allows emergency routines to be exec uted for system recovery or to perform system shut down. 1) sak product variant does not support power-down mode.
xc87xclm functional description data sheet 76 v1.5, 2011-03 figure 20 cgu block diagram direct drive (pll bypass operation) during pll bypass operation, t he system clock has the same frequency as the external clock source. (3.1) pll mode the cpu clock is derived from the oscillato r clock, divided by the nr factor (pdiv), multiplied by the nf factor ( ndiv), and divided by the od fa ctor (kdiv). pll output must pll pll core lock detect nf:1 nr:1 fvco fn fp osc fosc od:1 f sys ndiv pll_lock pllbyp kdiv pdiv wrapper pll watchdog external oscillator watchdog pllpd extoscr oscss pllr switching circuitry osc sys f f =
xc87xclm functional description data sheet 77 v1.5, 2011-03 not be bypassed for this pll mode. th e pll mode is used during normal system operation. (3.2) system frequency selection for the xc87x, the value of nf, nr and od can be select ed by bits ndiv, pdiv and kdiv respectively for different oscillator inputs inorder to ob tain the required fsys. but the combination of these factors must fulfill t he following condition: ? 100 mhz < f vco <175mhz ? 800 khz < f osc / (2 * nr) < 8 mhz table 26 provides examples on how the typica l system frequency of fsys = 144 mhz and maximum frequency of 160 mhz (cpu clock = 26.67 mhz)can be obtained for the different oscillator sources. 3.8.1 recommended external oscillator circuits the oscillator circuit, a pierce oscillator, is designed to work with bot h, an external crystal oscillator or an external stable clock source. it basically consists of an inverting amplifier and a feedback element with xtal 1 as input, and xtal2 as output. when using a crystal, a proper external oscillator circuitr y must be con nected to both pins, xtal1 and xtal2. th e crystal frequency can be wit hin the range of 2 mhz to 20 mhz. additionally, it is necessa ry to have two load capacitances c x1 and c x2 , and depending on the crystal ty pe, a series resistor r x2 , to limit the current. a test resistor r q may be temporarily inserted to measure the oscillation allo wance (negative resistance) of the oscillator circuitry. r q values are typically specif ied by the crystal vendor. an external feedback resistor r f is also required in the extern al oscillator circuitry. the exact values and related operati ng range are dependent on the crystal frequency and have to be determined and optimized together with the crystal vendor using the negative table 26 system frequency ( f sys =144mhz) oscillator fosc n p k fsys on-chip 4 mhz 72 2 1 144 mhz 4 mhz 80 2 1 160 mhz external 8 mhz 72 4 1 144 mhz 6 mhz 72 3 1 144 mhz 4 mhz 72 2 1 144 mhz od x nr nf x f f osc sys =
xc87xclm functional description data sheet 78 v1.5, 2011-03 resistance method. oscillation measurement with the final target system is strongly recommended to verify the i nput amplitude at xtal1 and to determine the actual oscillation allowance (margi n negative resistan ce) for the oscillator-crystal system. when using an external clock si gnal, the signal must be co nnected to xtal1. xtal2 is left open (unconnected). the oscillator can also be us ed in combination with a ceramic re sonator. the final circuitry must also be verifi ed by the res onator vendor. figure 21 shows the recommended external oscillator circuitries fo r both operating mode s, external crystal mode and external input clock mode. figure 21 external os cillator circuitry note: for crystal operation, it is st rongly recommended to measure the negative resistance in the final target system (lay out) to determine t he optimum parameters for the oscillator operation. please refer to the mini mum and maximum values of the negative resistance specif ied by the crystal supplier. xc87x oscillator v ss c x1 2 - 20 mhz c x2 xtal1 xtal2 xc87x oscillator xtal1 xtal2 external clock signal f osc f osc fundamental mode crystal r x2 r q v ss r f
xc87xclm functional description data sheet 79 v1.5, 2011-03 3.8.2 clock management the cgu generates all clock signals required within the mi crocontroller from a single clock, f sys . during normal syst em operation, the typical fr equencies of the different modules are as follow: ? cpu clock: cclk, sclk = 24 mhz ? multican clock : mcanclk = 24 or 48 mhz ? mdu clock : mduclk = 24 or 48 mhz ? cordic clock : cordicclk = 24 or 48 mhz ? ccu6 clock : ccu6clk = 24 or 48 mhz ? t2ccu clock : t2ccuclk = 24 or 48 mhz ? peripheral clock: pclk = 24 mhz in addition, different clock freq uencies can be output to pin clkout (p0.0 or p0.7). the clock output frequency, which is derived from the clock out put divider (bit corel), can further be divided by 2 using toggle latch (bit tl en is set to 1). th e resulting output frequency has a 50% duty cycle. figure 22 shows the clock dist ribution of the xc87x.
xc87xclm functional description data sheet 80 v1.5, 2011-03 figure 22 clock generation from f sys pll nf,nr,od fsys clkrel cclk sclk pclk core peripherals on-chip osc clkout fosc corel couts toggle latch tlen /2 multican mcan clk fccfg mdu mdu clk mduccfg /3 sd 1 0 cordic cordic clk cccfg ccu6 ccu6 clk ccuccfg t2ccu t2ccu clk t2ccfg fclk oscss external osc
xc87xclm functional description data sheet 81 v1.5, 2011-03 for power saving purposes, the clocks may be disabled or slowed down according to table 27 . table 27 system frequency ( f sys =144mhz) power saving mode action idle clock to the cpu is disabled. slow-down clocks to the cpu and all th e peripherals are divided by a common programmable factor defined by bit field cmcon.clkrel. power-down 1) 1) sak product variant does not support power-down mode. oscillator and pll are switched off.
xc87xclm functional description data sheet 82 v1.5, 2011-03 3.9 power saving modes the power saving modes of the xc87x prov ide flexible power consumption through a combination of te chniques, including: ? stopping the cpu clock ? stopping the clocks of i ndividual system components ? reducing clock speed of some peripheral components ? power-down of the entire system with fast restart capability after a reset, the ac tive mode (normal operating m ode) is selected by default (see figure 23 ) and the system runs in the main system clock freque ncy. from active mode, different power saving modes can be selected by software. they are: ? idle mode ? slow-down mode ? power-down mode figure 23 transition betw een power saving modes note: sak product variant does not support power-down mode. power-down idle active slow-down set pd bit set pd bit set idle bit set idle bit set sd bit clear sd bit any interrupt & sd=0 exint0/rxd pin & sd=0 exint0/rxd pin & sd=1 any interrupt & sd=1
xc87xclm functional description data sheet 83 v1.5, 2011-03 3.10 watchdog timer the watchdog timer (wdt) provides a high ly reliable and secure way to detect and recover from software or hardwa re failures. the wdt is reset at a regular interval that is predefined by the user . the cpu must service the wdt within this inte rval to prevent the wdt from causing an xc87x syst em reset. hence, routine service of the wdt confirms that the system is functioning properly. this ensures that an acci dental malfunction of the xc87x will be aborted in a user-specified time period. in debug mode, the wdt is def ault suspended and stops coun ting. therefore, there is no need to refresh t he wdt during debugging. features ? 16-bit watchdog timer ? programmable reload value fo r upper 8 bits of timer ? programmable window boundary ? selectable input frequency of f pclk /2 or f pclk /128 ? time-out detection wit h nmi generation and reset prew arning activation (after which a system reset will be performed) the wdt is a 16-bit timer incr emented by a count rate of f pclk /2 or f pclk /128. this 16-bit timer is realized as two concatenated 8-bi t timers. the upper 8 bits of the wdt can be preset to a user-programmable value via a wa tchdog service access in order to modify the watchdog expire time per iod. the lower 8 bits are reset on each service access. figure 24 shows the block diag ram of the wdt unit. figure 24 wdt block diagram wdtrel mux wdt low byte 1:2 clear wdt control 1:128 wdt high byte fnmiwdt wdtin f pclk logic enwdt enwdt_p wdtrst overflow/time-out control & window-boundary control wd twinb .
xc87xclm functional description data sheet 84 v1.5, 2011-03 if the wdt is not serviced bef ore the timer overflow, a syst em malfunction is assumed. as a result, the wdt nmi is triggered (asse rt fnmiwdt) and the reset prewarning is entered. the prewarni ng period lasts for 30 h count, after which the system is reset (assert wdtrst). the wdt has a ?programmable window bounda ry? which disallows any refresh during the wdt?s count-up. a refr esh during this win dow boundary constitutes an invalid access to the wdt, causing th e reset prewarning to be ent ered but without triggering the wdt nmi. the system will still be reset afte r the prewarning period is over. the window boundary is from 0000 h to the value obtained from the concatenati on of wdtwinb and 00 h . after being serviced, the wd t continues co unting up from the value ( * 2 8 ). the time period for an overflow of the wdt is programmable in two ways: ? the input frequency to the wdt can be sele cted to be either f pclk /2 or f pclk /128 ? the reload value wdtrel for the high by te of wdt can be pr ogrammed in register wdtrel the period, p wdt , between servicing the wdt and th e next overflow can be determined by the following formula: (3.3) if the window-boundary refresh featur e of the wdt is enabled, the period p wdt between servicing the wdt and the next overflow is shorte ned if wdtwinb is greater than wdtrel, see figure 25 . this period can be calculated using the same formula by replacing wdtrel with wdtwin b. for this feature to be useful, wdtwinb cannot be smaller than wdtrel. p wdt 2 1wdtin + 6 () 2 16 wdtrel ? 2 8 () f pclk --------------------------------------------------- -------------------------------------------------- - =
xc87xclm functional description data sheet 85 v1.5, 2011-03 figure 25 wdt timing diagram table 28 lists the possible watchdog time ranges that can be achiev ed using a certain module clock. some numbers are rounded to 3 significant digits. table 28 watchdog time ranges reload value in wdtrel prescaler for f pclk 2 (wdtin = 0) 128 (wdtin = 1) 24 mhz 24 mhz ff h 21.3 s1.37 ms 7f h 2.75 ms 176 ms 00 h 5.46 ms 350 ms wdtrel wdtwinb time count ffff h no refresh allowed refresh allowed
xc87xclm functional description data sheet 86 v1.5, 2011-03 3.11 multiplication/division unit the multiplication/divis ion unit (mdu) provides fast 16-bit multiplication, 16-bit and 32-bit division as well as sh ift and normalize features. it has been integrated to support the xc87x core in real-tim e control applications, whic h require fast mathematical computations. features ? fast signed/unsigned 16-bit multiplication ? fast signed/unsigned 32-bit di vide by 16-bit and 16-bit divide by 16-bit operations ? 32-bit unsigned no rmalize operation ? 32-bit arithmetic/logi cal shift operations table 29 specifies the number of clock cycles used for calculat ion in various operations. table 29 mdu operation characteristics operation result remainder n o. of clock cycles used for calculation signed 32-bit/16-bit 32-bit 16-bit 33 signed 16-bit/16bit 16-bit 16-bit 17 signed 16-bit x 16-bit 32-bit - 16 unsigned 32-bit/16-bit 32-bit 16-bit 32 unsigned 16-bit/16-bit 16-bit 16-bit 16 unsigned 16-bit x 16-bit 32-bit - 16 32-bit normalize - - no. of shifts + 1 (max. 32) 32-bit shift l/r - - no. of shifts + 1 (max. 32)
xc87xclm functional description data sheet 87 v1.5, 2011-03 3.12 cordic coprocessor the cordic coprocessor provides cpu wit h hardware support for the solving of circular (trigonometric), linear (multiply-a dd, divide-add) and hy perbolic functions. features ? modes of operation ? supports all cordic operatin g modes for solving circul ar (trigonometric), linear (multiply-add, divide-add) and hyperbolic functions ? integrated look-up tables (l uts) for all operating modes ? circular vectoring mode: ext ended support for values of in itial x and y data up to full range of [-2 15 ,(2 15 -1)] for solving angle and magnitude ? circular rotation mode: extended support for values of initial z data up to full range of [-2 15 ,(2 15 -1)], representing angles in the range [- ,((2 15 -1)/2 15 ) ] for solving trigonometry ? implementation-depen dent operational frequency of up to 80 mhz ? gated clock input to s upport disabling of module ? 16-bit accessible data width ? 24-bit kernel data width plus 2 overflow bits for x and y each ? 20-bit kernel data width plus 1 overflow bit for z ? with keep bit to retain the la st value in the kernel regi ster for a new calculation ? 16 iterations per calculation: approximately 41 cl ock-cycles or less, from set of start (st) bit to set of end-of-calculation flag, excludi ng time taken for write and read access of data bytes. ? twos complement data processing ? only exception: x result data with us er selectable option for unsigned result ? x and y data generally acce pted as integer or ratio nal number; x and y must be of the same data form ? entries of luts are 20-bit signed integers ? entries of atan and atanh luts are inte ger representations (s19) of angles with the scaling such that [-2 15 ,(2 15 -1)] represents the range [- ,((2 15 -1)/2 15 ) ] ? accessible z result data for circular and hy perbolic functions is integer in data form of s15 ? emulated lut fo r linear function ? data form is 1 integer bit and 15-bit fractional part (1.15) ? accessible z result data fo r linear function is rational number with fi xed data form of s4.11 (signed 4q16) ? truncation error ? the result of a cordic calc ulation may return an appr oximation due to truncation of lsbs ? good accuracy of the cordic calculated result data, especially in circular mode ? interrupt ? on completion of a calculation
xc87xclm functional description data sheet 88 v1.5, 2011-03 ? interrupt enabling a nd corresponding flag 3.13 uart and uart1 the xc87x provides two universal asynch ronous receiver/transmitter (uart and uart1) modules for full-duplex asynchron ous reception/transmission. both are also receive-buffered, i.e., they can commence reception of a second byte before a previously received byte has been read from the receive register. however, if the first byte still has not been read by the time rece ption of the second by te is complete, one of the bytes will be lost. features ? full-duplex asynchronous modes ? 8-bit or 9-bit data frames, lsb first ? fixed or vari able baud rate ? receive buffered ? multiprocessor communication ? interrupt generation on the completion of a data transmission or reception the uart modules can operate in the four modes shown in table 30 . there are several ways to ge nerate the baud rate clock fo r the serial port, depending on the mode in which it is operating. in mode 0, the baud rate for the transfer is fixed at f pclk /2. in mode 2, the baud rate is generated internally based on th e uart input clock and can be configured to either f pclk /32 or f pclk /64. for uart1 module, only f pclk /64 is available. the variable baud rate is set by the underflo w rate on the dedicated baud-rate generator. for uart module, t he variable baud rate alter natively can be set by the overflow rate on timer 1. 3.13.1 baud-rate generator both uart modules have their own dedicat ed baud-rate generator , which is based on a programmable 8-bit reload value, and in cludes divider stages (i.e., prescaler and table 30 uart modes operating mode baud rate mode 0: 8-bit shift register f pclk /2 mode 1: 8-bit shift uart variable mode 2: 9-bit shift uart f pclk /32 or f pclk /64 1) 1) for uart1 module, the baud rate is fixed at f pclk /64. mode 3: 9-bit shift uart variable
xc87xclm functional description data sheet 89 v1.5, 2011-03 fractional divider) for generating a wide ra nge of baud rates based on its input clock f pclk , see figure 26 . figure 26 baud-rate generator circuitry the baud rate timer is a count-down timer a nd is clocked by eith er the output of the fractional divider ( f mod ) if the fractional divider is enabled (fdcon.fden = 1), or the output of the prescaler ( f div ) if the fractional divider is disabled (fden = 0). for baud rate generation, the fractional di vider must be configured to fractional divider mode (fdcon.fdm = 0). this allows the baud rate contro l run bit bcon.r to be used to start or stop the baud ra te timer. at each time r underflow, the timer is reloaded with the 8-bit reload value in register bg and one clock pulse is genera ted for the serial channel. enabling the fractional divider in normal divider mode (fden = 1 and fdm = 1) stops the baud rate timer and nullifies t he effect of bit bcon.r. see section 3.14 . the baud rate ( f br ) value is dependent on th e following parameters: ? input clock f pclk ? prescaling factor (2 brpre ) defined by bit field br pre in register bcon ? fractional divider (step/256 ) defined by register fdstep (to be considered only if fractional divider is enab led and operatin g in fractional divider mode) ? 8-bit reload value (br_val ue) for the baud rate time r defined by register bg fdstep 1 fdm adder fdres fden&fdm clk fractional divider prescaler ndov ?0? fden 00 01 10 11 11 10 01 00 0 1 (overflow) 0 f br 8-bit baud rate timer 8-bit reload value r 0 1 f div f div f pcl k f mod
xc87xclm functional description data sheet 90 v1.5, 2011-03 the following formulas calculate the final baud rate without a nd with the fractional divider respectively: (3.4) (3.5) the maximum baud rate that can be generated is limited to f pclk /32. hence, for a module clock of 24 mhz, the maximum ac hievable baud rate is 0.75 mbaud. standard lin protocol can support a maximum baud rate of 20 kh z, the baud rate accuracy is not critical and the fractional divider can be disabled. only the prescaler is used for auto baud rate calcul ation. for lin fast mode, which support s the baud rate of 20 khz to 57.6 khz, t he higher baud rates re quire the use of the fractional divider for greater accuracy. table 31 lists the various common ly used baud rates with their corresponding parameter settings and deviation errors. the fractiona l divider is disabled and a module clock of 24 mhz is used. the fractional divider allows baud rates of hi gher accuracy (lower deviation error) to be generated. table 32 lists the resulting de viation errors from ge nerating a b aud rate of 57.6 khz, using different module clock freque ncies. the fractional divider is enabled (fractional divider mode) and the corresponding param eter settings are shown. table 31 typical baud rates for uart with fractional divider disabled baud rate prescaling factor (2brpre) reload value (br_value + 1) deviation error 19.2 kbaud 1 (brpre=000 b ) 78 (4e h )0.17% 9600 baud 1 (brpre=000 b ) 156 (9c h )0.17% 4800 baud 2 (brpre=001 b ) 156 (9c h )0.17% 2400 baud 4 (brpre=010 b ) 156 (9c h )0.17% baud rate f pclk 16 2 brpre br_value 1 + () ------------------------------------------ ----------------------------------------- where 2 brpre br_value 1 + () 1 > = baud rate f pclk 16 2 brpre br_value 1 + () ------------------------------------------------------ ----------------------------- step 256 -------------- - =
xc87xclm functional description data sheet 91 v1.5, 2011-03 3.13.2 baud rate generation using timer 1 in uart modes 1 and 3 of uart module, timer 1 can be used for generating the variable baud rates. in theo ry, this timer could be used in any of its modes. but in practice, it should be set into auto-reload mo de (timer 1 mode 2), with its high byte set to the appropriate value for the required b aud rate. the baud rate is determined by the timer 1 overflow rate and th e value of smod as follows: (3.6) 3.14 normal divider mode (8-bit auto-reload timer) setting bit fdm in register fdco n to 1 configures the fraction al divider to normal divider mode, while at the sa me time disables b aud rate generation (see figure 26 ). once the fractional divider is enabled (fden = 1), it f unctions as an 8-bit auto-reload timer (with no relation to baud rate gener ation) and counts up from the reload value with each input clock pulse. bit field result in register fdres represents the timer value, while bit field step in register fdstep defines the reload value. at eac h timer overflow, an overflow flag (fdcon.ndov) will be set and an interrupt requ est generated. this gives an output clock f mod that is 1/n of the input clock f div , where n is defined by 256 - step. the output frequency in normal divider mode is derived as follows: (3.7) table 32 deviation error for uart wi th fractional divider enabled f pclk prescaling factor (2brpre) reload value (br_value + 1) step deviation error 24 mhz 1 6 (6 h ) 59 (3b h ) +0.03 % 12 mhz 1 3 (3 h ) 59 (3b h ) +0.03 % 8mhz 1 2 (2 h ) 59 (3b h ) +0.03 % 6mhz 1 6 (6 h ) 236 (ec h ) +0.03 % mode 1, 3 baud rate 2 smod f pclk 32 2 256 th1 ? () ---------------------------------------------------- - = f mod f div 1 256 step ? ----------------------------- - =
xc87xclm functional description data sheet 92 v1.5, 2011-03 3.15 lin protocol the uart module can be used to support the local interc onnect network (lin) protocol for both master and slave operations. the lin baud rate detect ion feature, which consists of the hardware logic for break and synch byte detection, provides the capability to detect t he baud rate within lin protocol using timer 2. this allows the uart to be synchronized to the lin baud rate for data transmission and reception. note: the lin baud rate detection feature is available for use only with uart. to use uart1 for lin communication, software has to be implemented to detect the break and synch byte. lin is a holistic comm unication concept for local inte rconnected networks in vehicles. the communication is based on the sci (uart) data format, a single-master/multiple- slave concept, a clock synchronization fo r nodes without stab ilized time base. an attractive feature of lin is self-synchronization of the sl ave nodes without a crystal or ceramic resonator, which signif icantly reduces the co st of hardware pl atform. hence, the baud rate must be calc ulated and returned wit h every message frame. the structure of a li n frame is shown in figure 27 . the frame consists of the: ? header, which comprises a break ( 13-bit time low), synch byte (55 h ), and id field ? response time ? data bytes (according to uart protocol) ? checksum figure 27 structure of lin frame 3.15.1 lin header transmission lin header transmission is on ly applicable in master mode . in the lin communication, a master task decides when and which fram e is to be transferred on the bus. it also identifies a slave task to pr ovide the data trans ported by each frame. the information frame slot frame response response space header synch protected identifier data 1 data 2 data n checksum
xc87xclm functional description data sheet 93 v1.5, 2011-03 needed for the handshaking betw een the master and slave ta sks is provided by the master task through the header portion of the frame. the header consists of a break and synch pattern followed by an identifier. among these three fields, only the break pat tern cannot be transmitted as a normal 8-bit uart data. the break must contain a dominant value of 13 bits or more to ensure proper synchronization of slave nodes. in the lin communication, a slave task is r equired to be synchronized at the beginning of the protected identifier fi eld of frame. for this purpos e, every frame starts with a sequence consisting of a brea k field followed by a synch by te field. this sequence is unique and provides enough in formation for any slave task to detect the beginning of a new frame and be synchro nized at the start of the identifier field. upon entering lin communicat ion, a connection is establ ished and the transfer speed (baud rate) of the serial communication part ner (host) is automat ically synchronized in the following steps: step 1: initialize interface for recept ion and timer for ba ud rate measurement step 2: wait for an inco ming lin frame from host step 3: synchronize the baud rate to the host step 4: enter for master request frame or for slave response frame note: re-synchronization and setup of baud rate are always done for every master request header or slave re sponse header lin frame.
xc87xclm functional description data sheet 94 v1.5, 2011-03 3.16 high-speed synchronous serial interface the high-speed synchronou s serial interface (ssc ) supports full-duplex and half-duplex synchronou s communication. the serial clock signal can be generated by the ssc internally (master m ode), using its own 16-bit bau d-rate generator, or can be received from an external master (slave mode ). data width, shift di rection, clock polarity and phase are programmable. this allows communication with spi-compatible devices or devices using other sync hronous serial interfaces. features ? master and slave mode operation ? full-duplex or ha lf-duplex operation ? transmit and receive buffered ? flexible data format ? programmable number of data bits: 2 to 8 bits ? programmable shift directi on: lsb or msb shift first ? programmable clock polarity: idle lo w or high state for the shift clock ? programmable clock/data phase: data shift with leading or traili ng edge of the shift clock ? variable baud rate ? compatible with serial pe ripheral interface (spi) ? interrupt generation ? on a transmitter empty condition ? on a receiver full condition ? on an error condition (receive, p hase, baud rate, transmit error) data is transmitted or received on lines txd and rxd, which are normally connected to the pins mtsr (master transmit/slave re ceive) and mrst (ma ster receive/slave transmit). the clock signal is output via line ms_clk (master serial shift clock) or input via line ss_clk (slave serial shift clock). both lines are normally connected to the pin sclk. transmission and receptio n of data are double-buffered. figure 28 shows the block di agram of the ssc.
xc87xclm functional description data sheet 95 v1.5, 2011-03 figure 28 ssc block diagram pclk ss_clk rir tir eir receive int. request transmit int. request error int. request control status txd(mas ter) rxd(slave) shift clock ms_clk rxd(master) txd(slave) internal bus baud-rate generator clock control ssc control block register con pin control 16-bit shift register transmit buffer register tb receive buffer register rb
xc87xclm functional description data sheet 96 v1.5, 2011-03 3.17 timer 0 and timer 1 timer 0 and timer 1 can func tion as both timers or count ers. when functioning as a timer, timer 0 and timer 1 are incremented every machine cycle, i.e. every 2 input clocks (or 2 pclks). when functioning as a counter, timer 0 and timer 1 are incremented in response to a 1-to-0 transiti on (falling edge) at their respective external input pins, t0 or t1. timer 0 and 1 are fully compat ible and can be configured in four different operating modes for use in a vari ety of applications, see table 33 . in modes 0, 1 and 2, the two timers operate ind ependently, but in mo de 3, their functions are specialized. table 33 timer 0 and timer 1 modes mode operation 0 13-bit timer the timer is essentially an 8-bit c ounter with a divide-by-32 prescaler. this mode is included solely for co mpatibility with in tel 8048 devices. 1 16-bit timer the timer registers, tlx and thx, are concatenated to form a 16-bit counter. 2 8-bit timer with auto-reload the timer register tlx is reloaded with a user-def ined 8-bit value in thx upon overflow. 3 timer 0 operates as two 8-bit timers the timer registers, tl0 and th0, ope rate as two separat e 8-bit counters. timer 1 is halted and retain s its count ev en if enabled.
xc87xclm functional description data sheet 97 v1.5, 2011-03 3.18 timer 2 and timer 21 timer 2 and timer 21 ar e 16-bit general purpose timers (t hl2) that are fully compatible and have two modes of oper ation, a 16-bit auto-reload mode and a 16-bi t one channel capture mode, see table 34 . as a timer, the timers count with an input clock of pclk/12 (if prescaler is disabled). as a counter, they count 1-to-0 transitions on pin t2. in the counter mode, the maximum resolution for the count is pclk/24 (if prescaler is disabled). table 34 timer 2 modes mode description auto-reload up/down count disabled ? count up only ? start counting from 16-bit reload value, overflow at ffff h ? reload event confi gurable for trigger by overflow condition only, or by negative/positive edge at input pin t2ex as well ? programmble reload value in register rc2 ? interrupt is generate d with reload event up/down count enabled ? count up or down, direction dete rmined by level at input pin t2ex ? no interrupt is generated ? count up ? start counting from 16-bit re load value, overflow at ffff h ? reload event triggered by overflow condition ? programmble reload value in register rc2 ? count down ? start counting from ffff h , underflow at value defined in register rc2 ? reload event trigger ed by underflow condition ? reload value fixed at ffff h channel capture ? count up only ? start counting from 0000 h , overflow at ffff h ? reload event triggered by overflow condition ? reload value fixed at 0000 h ? capture event triggered by falling/rising ed ge at pin t2ex ? captured timer value st ored in register rc2 ? interrupt is gene rated with reload or capture event
xc87xclm functional description data sheet 98 v1.5, 2011-03 3.19 timer 2 capture/compare unit the t2ccu (timer 2 capture/compare unit) co nsists of the standard timer 2 unit and a capture/compare unit (ccu) . the capture/compare time r (cct) is part of the ccu. control is available in th e t2ccu to select individual ly for each of its 16-bit capture/compare channel, eit her the timer 2 or the capt ure/compare timer (cct) as the time base. both timers have a resolution of 16 bi ts.the clock frequency of t2ccu, f t2ccu , could be set at pclk frequency or 2 times the pclk frequency. the t2ccu can be used for various digital si gnal generation and event capturing like pulse generation, pul se width modulation, pulse width meas uring etc. target applications include various automotive control as well as industrial (frequency generation, digital-to-analog c onversion, process control etc.). t2ccu features ? option to select individually for each channel, either timer 2 or capture/compare timer as time base ? extremely flexible capture/compare time r count rate by cascading with timer 2 ? capture/compare timer may be ?reset? i mmediately by triggering overflow event ? 16-bit resolution ? six compare channels in total ? four capture channels mu ltiplexed with the compar e channels, in total ? shadow register for each compare register ? transfer via software control or on timer overflow. ? compare mode 0: compare output signal c hanges from the inacti ve level to active level on compare match. returns to inactive level on timer overflow. ? active level can be defined by regi ster bit for cha nnel groups a and b. ? support of 0% to 100% duty cycle in compare mode 0. ? compare mode 1: full control of the softwa re on the compare output signal level, for the next compare match. ? concurrent compare mo de with channel 0 ? capture mode 0: capture on any external event (rising/fallin g/both edge) at the 4 pins t2cc0 to t2cc3. ? capture mode 1: capture upon writing to the low byte of the corresponding channel capture register. ? capture mode 0 or 1 can be established independently on the 4 capture channels.
xc87xclm functional description data sheet 99 v1.5, 2011-03 3.20 capture/compare unit 6 the capture/compare unit 6 (ccu6) provides two independent timers (t12, t13), which can be used for pulse width modulation (p wm) generation, especially for ac-motor control. the ccu6 also supports specia l control modes for block commutation and multi-phase machines. the timer t12 can function in capture and/or comp are mode for its three channels. the timer t13 can work in compare mode only. the multi-channel control unit generates output patterns, whic h can be modulated by t12 and/or t13. the modulation sources can be select ed and combined for the signal modulation. timer t12 features ? three capture/compare channels, each ch annel can be used eit her as a capture or as a compare channel ? supports generation of a three-phase pwm (six outputs, indi vidual signals for highside and lowside switches) ? 16-bit resolution, maximum count fr equency = peripheral clock frequency ? dead-time control for each channel to av oid short-circuits in the power stage ? concurrent update of the required t12/13 registers ? generation of cente r-aligned and edge-aligned pwm ? supports single-shot mode ? supports many interr upt request sources ? hysteresis-like control mode timer t13 features ? one independent compar e channel with one output ? 16-bit resolution, maximum count fr equency = peripheral clock frequency ? can be synchronized to t12 ? interrupt generation at per iod-match and compare-match ? supports single-shot mode additional features ? implements block commutati on for brushless dc-drives ? position detection vi a hall-sensor pattern ? automatic rotational speed meas urement for block commutation ? integrated error handling ? fast emergency stop without cpu load via external signal (ctrap ) ? control modes for multi-channel ac-drives ? output levels can be selected and adapted to the power stage the block diagram of the ccu6 module is shown in figure 29 .
xc87xclm functional description data sheet 100 v1.5, 2011-03 figure 29 ccu6 block diagram channel 0 channel 1 channel 2 t12 dead- time control input / output control cc62 co ut62 cc61 co ut61 cc60 co ut60 co ut63 ct rap channel 3 t13 ccpos0 1 1 1 2 2 2 1 start compare capture 3 multi- channel control address decoder clock control interrupt control trap control compare compar e compar e compar e 1 trap input port control ccpos1 ccpos2 output select output select 3 hall input module kernel ccu6_block_diagram t13hr t12hr
xc87xclm functional description data sheet 101 v1.5, 2011-03 3.21 controller area network (multican) the multican module contains two fu ll-can nodes operat ing independently or exchanging data and remote fr ames via a gateway function . transmission and reception of can frames is handled in accordance to can specification v2.0 b active. each can node can receive and transmit st andard frames with 11-bit i dentifiers as well as extended frames with 29-bit identifiers. both can nodes share a comm on set of message objects, where each message object may be individually allocated to one of the can nodes. besides serving as a storage container for incoming and outgoing frames, message objects may be combined to build gateways between the can nodes or to setup a fifo buffer. the message objects are organ ized in double chained lists , where each can node has it?s own list of message objects. a can nod e stores frames only into message objects that are allocated to the list of the can no de. it only transmits me ssages from objects of this list. a powerful, command driven li st controller performs all list operations. the bit timings for the can nodes are derived from the peripheral clock ( f can ) and are programmable up to a da ta rate of 1 mbaud. a pair of receive and transmit pins connects each can node to a bus transceiver. figure 30 overview of the multican features ? compliant to iso 11898. multican module kernel mult ic an _xc 8_overview port control can node 0 can control message object buffer 32 objects can node 1 txdc0 rxdc0 txdc1 rxdc1 linked list control f can clock control address decoder & data control access mediator interrupt controller cansrc[7:0] a[13: 2] d[31:0]
xc87xclm functional description data sheet 102 v1.5, 2011-03 ? can functionality according to can specification v2.0 b active. ? dedicated control registers ar e provided for each can node. ? a data transfer rate up to 1 mbaud is supported. ? flexible and powerful message transfer c ontrol and error hand ling capabilities are implemented. ? advanced can bus bit timing analysis and baud rate detection can be performed for each can node via th e frame counter. ? full-can functionality: a set of 32 message objects can be individually ? allocated (assigned ) to any can node ? configured as transmit or receive object ? setup to handle frames with 11-bit or 29-bit identifier ? counted or assigned a time stamp via a frame counter ? configured to remote monitoring mode ? advanced accept ance filtering: ? each message object provid es an individual acceptan ce mask to filter incoming frames. ? a message object can be configured to accept only standard or only extended frames or to accept both st andard and ex tended frames. ? message objects can be grouped into 4 priority classes. ? the selection of the message to be tran smitted first can be performed on the basis of frame identifier, ide bit and rtr bit according to can arbitration rules. ? advanced message ob ject functionality: ? message objects can be combined to build fifo message buffers of arbitrary size, which is only limited by th e total number of message objects. ? message objects can be linked to form a gateway to automatically transfer frames between 2 different can buses. a single gateway can link any two can nodes. an arbitrary number of gateways may be defined. ? advanced data management: ? the message objects are org anized in double chained lists. ? list reorganizations may be performed an y time, even during full operation of the can nodes. ? a powerful, command driven list contro ller manages the organ ization of the list structure and ensures co nsistency of the list. ? message fifos are based on the list structure and can easily be scaled in size during can operation. ? static allocation commands offer compatibility with tw incan applications, which are not list based. ? advanced interrupt handling: ? up to 8 interrupt output lines are available. most interrupt requests can be individually routed to one of the 8 interrupt output lines. ? message postprocessing notifications c an be flexibly aggregat ed into a dedicated register field of 64 notification bits.
xc87xclm functional description data sheet 103 v1.5, 2011-03 3.22 analog-to-digital converter the xc87x includes a high-performance 10-bit analog-to-digital converter (adc) with eight multiplexed analog input channels. the adc uses a successive approximation technique to convert t he analog voltage levels from up to eight different sources. the analog input channel s of the adc are available at an0 - an7. features ? successive approximation ? 8-bit or 10-bit resolution ? eight analog channels ? four independent result registers ? result data protection for slow cpu access (wait-for-read mode) ? single conversion mode ? autoscan functionality ? limit checking for conversion results ? data reduction filter (accumulation of up to 2 conversion results) ? two independent conversion request sources with programmable priority ? selectable conversion request trigger ? flexible interrupt generation wi th configurable service nodes ? programmable sample time ? programmable clock divider ? cancel/restart feature for running conversions ? integrated sample and hold circuitry ? compensation of offset errors ? low power modes 3.22.1 adc clocking scheme a common module clock f adc generates the various clock si gnals used by the analog and digital parts of the adc module: ? f adca is input clock for the analog part. ? f adci is internal clock for the analog part (defin es the time base for conversion length and the sample time). this clock is generat ed internally in the analog part, based on the input clock f adca to generate a correct duty cycle for the analog components. ? f adcd is input clock for the digital part. figure 31 shows the clocking scheme of the adc module. the prescaler ratio is selected by bit field ctc in register glob ctr. a prescaling ratio of 32 can be selected when the maximum performance of the adc is not required.
xc87xclm functional description data sheet 104 v1.5, 2011-03 figure 31 adc clocking scheme for module clock f adc = 24 mhz, the analog clock f adci frequency can be selected as shown in table 35 . during slow-down mode, f adc may be reduced further, for example, to 12 mhz or 6 mhz. however, it is important to note that the conversion error could increase due to loss of charges on the capacitors, if f adc becomes too low during slow-down mode. 3.22.2 adc conversion sequence the analog-to-digital conversion procedu re consists of th e following phases: table 35 f adci frequency selection module clock f adc ctc prescaling ratio analog clock f adci 24 mhz 00 b 2 12mhz 01 b 3 8mhz 10 b 4 6mhz 11 b (default) 32 750 khz analog components f adci f adc = f pclk mux arbiter registers interrupts analog part digital part f adcd f adca 32 clock prescaler ctc 2
xc87xclm functional description data sheet 105 v1.5, 2011-03 ? synchronization phase ( t syn ) ? sample phase ( t s ) ? conversion phase ? write result phase ( t wr ) figure 32 adc conversion timing t s t conv t wr sample bit busy bit conversion phase sample phase write result phase conversion start trigger source interrupt result interrupt t syn channel interrupt f adci
xc87xclm functional description data sheet 106 v1.5, 2011-03 3.23 on-chip debug support the on-chip debug support (ocds ) provides the basic functionality required for the software development and debugging of xc800-based systems. the ocds design is based on these principles: ? use the built-in debug func tionality of the xc800 core ? add a minimum of hardware overhead ? provide support for mo st of the operations by a monitor program ? use standard interfaces to communicate with the host (a debugger) features ? set breakpoints on instruction addre ss and on address ra nge within the program memory ? set breakpoints on internal ram address range ? support unlimited software brea kpoints in flash/ram code region ? process external breaks via jtag and upon activating a dedicated pin ? step through the program code the ocds functional blocks are shown in figure 33 . the monitor mo de control (mmc) block at the center of ocds system brings together control sign als and supports the overall functionality. the mmc communicates with the xc800 core, primarily via the debug interface, and also receives reset and clock signals. after processing memory address and control signals from the core, the mmc provides proper access to the dedicated extra-memo ries: a monitor rom (holding the code) and a monitor ram (for work -data and monitor-stack). the ocds system is a ccessed through the jtag 1) , which is an interface dedicated exclusively for testing a nd debugging activities and is not normally used in an application. the dedica ted mbc pin is used for exter nal configurati on and debugging control. note: all the debug func tionality described he re can normally be used only after xc87x has been started in ocds mode. 1) the pins of the jtag port can be assigned to either t he primary port (port 0) or ei ther of the secondary ports (ports 1 and 2/port 5). user must set the jtag pins (tck and tdi) as input during connection with the ocds system.
xc87xclm functional description data sheet 107 v1.5, 2011-03 figure 33 ocds block diagram 3.23.1 jtag id register this is a read-only register located inside the jtag module, and is used to recognize the device(s) connected to the jtag interface. its content is shifted out when instruction register contains the idcode command (opcode 04 h ), and the same is also true immediately after reset. the jtag id register co ntents for the xc87x flas h devices are given in table 36 . note: the asterisk (*) abo ve denotes all possible device configurations. table 36 jtag id summary device type device name jtag id flash xc87x*-16ff 1018 2083 h xc87x*-13ff 1018 3083 h jtag module monitor & bootstrap loader control line jtag memory control unit user program memory xc800 core prog & iram addresses debug interface reset clock tms tck tdi tdo tck tdi tdo control memory control debug interface system control unit boot/ monitor rom monitor ram user internal ram reset reset clock prog data monitor mode control mbc - parts of ocds suspend control ocds_xc886c-block_diagram-um-v0.2
xc87xclm functional description data sheet 108 v1.5, 2011-03 3.24 chip identification number the xc87x identity (id) register is located at pa ge 1 of address b3 h . the value of id register is 49 h . however, for easy identificati on of product variants, the chip identification number, which is an unique number assigned to each product variant, is available. the differentiati on is based on the product, variant type and device step information. two methods are provided to read a device?s chip ident ification number: ? in-application subroutine, get_chip_info ? bootstrap loader (bsl) mode a table 37 lists the chip identifica tion numbers of available xc 87x flash device variants. table 37 chip identification number product variant chip id entification number ac-step flash devices xc878-16ff 5v 4b580063 h xc878m-16ff 5v 4b580023 h xc878cm-16ff 5v 4b580003 h xc878lm-16ff 5v 4b500023 h xc878clm-16ff 5v 4b500003 h xc878-13ff 5v 4b590463 h xc878m-13ff 5v 4b590423 h xc878cm-13ff 5v 4b590403 h xc878lm-13ff 5v 4b510423 h xc878clm-13ff 5v 4b510403 h xc878-16ff 3v3 4b180063 h xc878m-16ff 3v3 4b180023 h xc878cm-16ff 3v3 4b180003 h xc878-13ff 3v3 4b190463 h xc878m-13ff 3v3 4b190423 h xc878cm-13ff 3v3 4b190403 h xc874cm-16fv 5v 4b580002 h xc874lm-16fv 5v 4b500022 h xc874-16fv 5v 4b580062 h
xc87xclm functional description data sheet 109 v1.5, 2011-03 xc874cm-13fv 5v 4b590402 h xc874lm-13fv 5v 4b510422 h xc874-13fv 5v 4b590462 h table 37 chip identification number (cont?d) product variant chip id entification number ac-step
xc87xclm electrical parameters data sheet 108 v1.5, 2011-03 4 electrical parameters chapter 4 provides the characteristics of the electrical par ameters which are implementation-specific for the xc87x. 4.1 general parameters the general parameters are described here to aid the us ers in interpreting the parameters mainly in section 4.2 and section 4.3 . 4.1.1 parameter interpretation the parameters listed in this section repres ent partly the characteristics of the xc87x and partly its requirements on the system. to aid interpre ting the parameters easily when evaluating them for a design, they are indicated by the abbreviations in the ?symbol? column: ? cc these parameters indicate c ontroller c haracteristics, which are distinctive features of the xc87x and must be regarded for a system design. ? sr these parameters indicate s ystem r equirements, which must be provided by the microcontroller system in whic h the xc87x is designed in.
xc87xclm electrical parameters data sheet 109 v1.5, 2011-03 4.1.2 absolute maximum rating maximum ratings are the extreme limits to wh ich the xc87x can be subjected to without permanent damage. note: stresses above thos e listed under ?absolute ma ximum ratings? may cause permanent damage to the device. this is a stre ss rating only and functional operation of the device at these or any other condition s above those indicated in the operational sections of th is specification is not impl ied. exposure to absolute maximum rating conditions for exten ded periods may affect device reliability. during absolute maximum rating overload conditions ( v in > v ddp or v in < v ss ) the voltage on v ddp pin with respect to ground ( v ss ) must not exceed the values defined by the absolute maximum ratings. table 38 absolute maximu m rating parameters parameter symbol limit values unit notes min. max. ambient temperature t a -40 125 c under bias storage temperature t st -65 150 c junction temperature t j -40 140 c under bias voltage on power supply pin with respect to v ss v ddp -0.5 6 v voltage on any pin with respect to v ss v in -0.5 v ddp + 0.5 or max. 6 v whatever is lower input current on any pin during overload condition i in -10 10 ma absolute sum of all input currents during overload condition | i in |? 50 ma
xc87xclm electrical parameters data sheet 110 v1.5, 2011-03 4.1.3 operating conditions the following operating conditi ons must not be exceeded in order to ensure correct operation of the xc87x. all parameters ment ioned in the following table refer to these operating conditions, unless otherwise noted. table 39 operating condition parameters parameter symbol limit values unit notes/ conditions min. max. digital power supply voltage v ddp 4.5 5.5 v 5v device digital power supply voltage v ddp 3.0 3.6 v 3.3v device digital ground voltage v ss 0v cpu clock frequency 1) 1) f cclk is the input frequency to the xc800 core. please refer to figure 22 for detailed description. f cclk 26.67 2) 2) default setting of f cclk upon reset is 24 mhz. mhz ambient temperature t a -40 85 c saf-xc878/874... -40 105 c sax-xc878... -40 125 c sak-xc878/874...
xc87xclm electrical parameters data sheet 111 v1.5, 2011-03 4.2 dc parameters the electrical characteristics of the dc parameters are detaile d in this section. 4.2.1 input/output characteristics table 40 provides the characteristics of the input/output pins of the xc87x. table 40 input/output characteristi cs (operating conditions apply) parameter symbol limit values unit test conditions min. max. v ddp = 5 v range output low voltage v ol cc ? 0.6 v i ol = 9 ma (ds = 0) 1) i ol =12ma (ds=1) 2) output high voltage v oh cc 2.4 ? v i oh = -20 ma (ds = 0) 1) i oh = -25 ma (ds = 1) 2) input low voltage v il sr -0.3 0.8 v cmos mode input high voltage v ih sr 2.2 v ddp v cmos mode input hysteresis hys cc 0.35 ? v cmos mode 3)7) input low voltage at xtal1 v ilx sr -0.3 0.8 v input high voltage at xtal1 v ihx sr 3.4 v ddp v pull-up current i pu sr ? -20 a v ih,min -88 ? a v il,max pull-down current i pd sr ? 10 a v il,max 66 ? a v ih,min input leakage current i oz1 cc -1 1 a0 < v in < v ddp , t a 105 c 4) overload current on any pin i ov sr -5 5 ma absolute sum of overload currents | i ov |sr? 25 ma 5) voltage on any pin during v ddp power off v po sr ? 0.3 v 6)
xc87xclm electrical parameters data sheet 112 v1.5, 2011-03 maximum current per pin (excluding v ddp and v ss ) i m sr sr ? 25 ma maximum current for all pins (excluding v ddp and v ss ) | i m |sr? 150 ma maximum current into v ddp i mvddp sr ? 200 ma 5) maximum current out of v ss i mvss sr ? 200 ma 5) v ddp = 3.3 v range output low voltage v ol cc ? 0.5 v i ol = 6 ma (ds = 0) 1) i ol = 8 ma (ds = 1) 2) output high voltage v oh cc 2.2 ? v i oh =-5ma (ds=0) 1) i oh =-7ma (ds=1) 2) input low voltage v il sr -0.3 0.7 v cmos mode input high voltage v ih sr 2 v ddp v cmos mode input hysteresis hys cc 0.28 ? v cmos mode 3)7) input low voltage at xtal1 v ilx sr -0.3 0.7 v input high voltage at xtal1 v ihx sr 2.3 v ddp v pull-up current i pu sr ? -7 a v ih,min -35 ? a v il,max pull-down current i pd sr ? 12 a v il,max 60 ? a v ih,min input leakage current i oz1 cc -1 1 a0 < v in < v ddp , t a 105 c 4) overload current on any pin i ov sr -5 5 ma absolute sum of overload currents | i ov |sr? 25 ma 5) table 40 input/output characteristi cs (operating conditions apply) (cont?d) parameter symbol limit values unit test conditions min. max.
xc87xclm electrical parameters data sheet 113 v1.5, 2011-03 voltage on any pin during v ddp power off v po sr ? 0.3 v 6) maximum current per pin (excluding v ddp and v ss ) i m sr sr ? 8 ma maximum current for all pins (excluding v ddp and v ss ) | i m |sr? 150 ma maximum current into v ddp i mvddp sr ? 200 ma 5) maximum current out of v ss i mvss sr ? 200 ma 5) 1) ds = 0 refers to the pin having a weak drive st rength which is programmable via px_ds register. 2) ds = 1 refers to the pin having a strong drive st rength which is programmable via px_ds register. 3) not subjected to production test, verified by design/char acterization. hysteresis is implemented to avoid meta stable states and switching due to internal ground bounce. it cannot be guaranteed that it suppresses switching due to external system noise. 4) an additional error current ( i inj ) will flow if an overload current flows through an adjacent pin. tms pin and reset pin have internal pull devices and are not incl uded in the input leakage current characteristic. 5) not subjected to production test, verified by design/characterization. 6) not subjected to production test, verified by design/char acterization. however, for applications with strict low power-down current requirements, it is mandatory that no active voltage source is supplied at any gpio pin when v ddp is powered off. 7) p0.1 has a minimum input hysteresis of 0.25v. table 40 input/output characteristi cs (operating conditions apply) (cont?d) parameter symbol limit values unit test conditions min. max.
xc87xclm electrical parameters data sheet 114 v1.5, 2011-03 4.2.2 supply threshold characteristics table 41 provides the characteristics of the supply threshold in the xc87x. figure 34 supply th reshold parameters table 41 supply threshold parameters (operating conditions apply) parameters symbol limit values unit min. typ. max. v ddc brownout voltage 1) 1) detection is enabled in both active and power-down mode. v ddcbo cc 1.7 1.9 2.2 v ram data retention voltage v ddcrdr cc1.2??v v ddp prewarning voltage 2) 2) detection is enabled for 5.0v power supply variant. detection is disabled for 3.3v power supply variant. v ddppw cc 3.8 4.2 4.5 v power-on reset voltage 1)3) 3) the reset of evr is extended by 300 s typically after the vddc reaches the power-on reset voltage. v ddcpor cc 1.7 1.9 2.2 v vddp vddc v ddppw v ddcpor v ddcbo 5.0v 2.5v v ddcrdr
xc87xclm electrical parameters data sheet 115 v1.5, 2011-03 4.2.3 adc characteristics the values in the table be low are given for an analog power supply bet ween 4.5 v to 5.5 v. the adc can be used wit h an analog power supply down to 3 v. but in this case, the analog parame ters may show a reduced perf ormance. all ground pins ( v ss ) must be externally connected to one single star point in the sy stem. the voltage difference between the ground pins must not exceed 200mv. table 42 adc characteristics (o perating conditions apply; v ddp = 5v range) parameter symbol limit values unit test conditions/ remarks min. typ . max. analog reference voltage v aref sr v agnd + 1 v ddp v ddp + 0.05 v 1) analog reference ground v agnd sr v ss - 0.05 v ss v aref - 1 v 1) analog input voltage range v ain sr v agnd ? v aref v adc clocks f adc ? 24 ? mhz module clock 1) f adci ??14 2) mhz internal analog clock 1) see figure 31 sample time t s cc (2 + inpcr0.stc) t adci s 1) conversion time t c cc see section 4.2.3.1 s 1) differential nonlinearity |ea dnl | cc ? ? 1.5 lsb 10-bit conversion integral nonlinearity |ea inl | cc ? ? 2 lsb 10-bit conversion offset |ea off | cc ? ? 3 lsb 10-bit conversion gain |ea gain | cc ? ? 2.5 lsb 10-bit conversion switched capacitance at the reference voltage input c arefsw cc ? 10 14 pf 1)3) switched capacitance at the analog voltage inputs c ainsw cc ? 4 5 pf 1)4)
xc87xclm electrical parameters data sheet 116 v1.5, 2011-03 input resistance of the reference input r aref cc ? 1 2 k ? 1) input resistance of the selected analog channel r ain cc ? 1 3 k ? 1) 1) not subjected to production test, verified by design/characterization. 2) this value includes the maximum oscillator deviation. 3) this represents an equivalent switched capacitance. this capacitance is not switched to the reference voltage at once. instead of this, smaller capacitances are successively switched to the reference voltage. 4) the sampling capacity of the conversion c-network is pre-charged to v aref /2 before connecting the input to the c-network. because of the parasitic elements, the voltage measured at anx is lower than v aref /2. table 42 adc characteristics (o perating conditions apply; v ddp = 5v range) parameter symbol limit values unit test conditions/ remarks min. typ . max.
xc87xclm electrical parameters data sheet 117 v1.5, 2011-03 figure 35 adc input circuits 4.2.3.1 adc conversion timing conversion time, t c = t adc ( 1 + r (3+n+stc) ) , where r=ctc+2 for ctc=00 b , 01 b or 10 b , r = 32 for ctc = 11 b , ctc = conversion time co ntrol (globctr.ctc), stc = sample time control (inpcr0.stc), n = 8 or 10 (for 8-bit and 10 -bit conversion respectively), t adc =1/ f adc v agndx r ext analog input circuitry v ain c ext anx c ainsw r ain, on v agndx reference voltage input circuitry c arefsw r aref, on v arefx v aref
xc87xclm electrical parameters data sheet 118 v1.5, 2011-03 4.2.4 power supply current table 43 , table 44 , table 45 and table 46 provide the characte ristics of the power supply current in the xc87x. table 43 power supply curre nt parameters (operati ng conditions apply; v ddp = 5v range) parameter symbol limit values unit test conditions typ. 1) 1) the typical i ddp values are based on preliminary measurements and are to be used as reference only. these values are periodically measured at t a =+25 c and v ddp =5.0v. max. 2) 2) the maximum i ddp values are measured under worst case conditions ( t a = + 105 c and v ddp =5.5v). v ddp = 5v range active mode i ddp 37.5 45 ma 3) saf and sax variants 3) i ddp (active mode) is measured with: cpu clock and in put clock to all peripherals running at 24 mhz with on- chip oscillator of 4 mhz, reset = v ddp ; all other pins are disconnected, no load on ports. 40.5 48 ma 3) sak variant idle mode i ddp 29.2 35 ma 4) saf and sax variants 4) i ddp (idle mode) is measured with: cpu clock disabled, wa tchdog timer disabled, input clock to all peripherals enabled and running at 24 mhz, reset = v ddp ; all other pins are disconnected, no load on ports. 32.2 38 ma 4) sak variant active mode with slow- down enabled i ddp 10 15 ma 5) saf and sax variants 5) i ddp (active mode with slow-down mode) is measured wi th: cpu clock and input clock to all peripherals running at 1 mhz by setting clkrel in cmcon to 1000 b , reset = v ddp ; all other pins are disconnected, no load on ports. 13 18 ma 5) sak variant idle mode with slow- down enabled i ddp 9.2 14 ma 6) saf and sax variants 6) i ddp (idle mode with slow-down mode) is measured with : cpu clock disabled, wa tchdog timer disabled, input clock to all peripherals enabled and running at 1 mhz by setting clkrel in cmcon to 1000 b , reset = v ddp ; all other pins are disconnected, no load on ports. 12.2 17 ma 6) sak variant
xc87xclm electrical parameters data sheet 119 v1.5, 2011-03 table 44 power down current 1) (operating conditions apply; v ddp = 5v range) 1) the table is only applicable to saf and sax va riants. sak variant does not support power-down mode parameter symbol limit values unit test conditions typ. 2) 2) the typical i pdp values are based on preliminary measurements and are to be used as reference only. these values are measured at v ddp =5.0v. max. 3) 3) the maximum i pdp values are measured at v ddp =5.5v. v ddp = 5v range power-down mode i pdp 20 80 a t a =+25 c 4)5) 4) i pdp has a maximum value of 450 a at t a = + 105 c. 5) i pdp is measured with: reset = v ddp , v agnd = v ss , rxd/int0 = v ddp ; rest of the ports are programmed to be input with either internal pull devices enabled or driven externally to ensure no floating inputs. - 250 a t a =+85 c 5)6) 6) not subjected to production test, verified by design/characterization.
xc87xclm electrical parameters data sheet 120 v1.5, 2011-03 table 45 power supply current parameters 1) (operating conditions apply; v ddp = 3.3v range) 1) the table is only applicable to saf and sax variants. parameter symbol limit values unit test conditions typ. 2) 2) the typical i ddp values are based on preliminary measurements and are to be used as reference only. these values are periodically measured at t a =+25 c and v ddp =3.3v. max. 3) 3) the maximum i ddp values are measured under worst case conditions ( t a = + 105 c and v ddp =3.6v). v ddp = 3.3v range active mode i ddp 35.4 43 ma 4) 4) i ddp (active mode) is measured with: cpu clock and input clock to all peripherals running at 24 mhz with on- chip oscillator of 4 mhz, reset = v ddp ; all other pins are disconnected, no load on ports. idle mode i ddp 27.6 33 ma 5) 5) i ddp (idle mode) is measured with: cpu clock disabled, watchdog timer disabled, input clock to all peripherals enabled and running at 24 mhz, reset = v ddp ; all other pins are disconnected, no load on ports. active mode with slow-down enabled i ddp 8.6 13 ma 6) 6) i ddp (active mode with slow-down mode) is measured with : cpu clock and input clock to all peripherals running at 1 mhz by setting clkrel in cmcon to 1000 b , reset = v ddp ; all other pins are disconnected, no load on ports. idle mode with slow-down enabled i ddp 812ma 7) 7) i ddp (idle mode with slow-down mode) is measured with: cpu clock disabled, watchdog timer disabled, input clock to all peripherals enabled and running at 1 mhz by setting clkrel in cmcon to 1000 b , reset = v ddp ; all other pins are disconnected, no load on ports.
xc87xclm electrical parameters data sheet 121 v1.5, 2011-03 table 46 power down current 1) (operating cond itions apply; v ddp = 3.3v range) 1) the table is only applicable to saf and sax variants. parameter symbol limit values unit test conditions typ. 2) 2) the typical i pdp values are based on preliminary measurements and are to be used as reference only. these values are measured at v ddp =3.3v. max. 3) 3) the maximum i pdp values are measured at v ddp =3.6v. v ddp = 3.3v range power-down mode i pdp 20 80 a t a =+25 c 4)5) 4) i pdp has a maximum value of 450 a at t a = + 105 c. 5) i pdp is measured with: reset = v ddp , v agnd = v ss , rxd/int0 = v ddp ; rest of the ports are programmed to be input with either internal pull devices enabled or driven externally to ensure no floating inputs. - 250 a t a =+85 c 5)6) 6) not subjected to production test, verified by design/characterization.
xc87xclm electrical parameters data sheet 122 v1.5, 2011-03 4.3 ac parameters the electrical characteristics of the ac parameters are detaile d in this section. 4.3.1 testing waveforms the testing waveforms for rise /fall time, output delay an d output high impedance are shown in figure 36 , figure 37 and figure 38 . figure 36 rise/fall time parameters figure 37 testing waveform, output delay figure 38 testing waveform, output high impedance 10% 90% 10% 90% v ss v ddp t r t f v dde / 2 te st p oin ts v dde / 2 v ss v ddp v load + 0.1 v v oh - 0.1 v timing reference points v load - 0.1 v v ol - 0.1 v
xc87xclm electrical parameters data sheet 123 v1.5, 2011-03 4.3.2 output rise/fall times table 47 provides the characteristics of the output rise/fall ti mes in the xc87x. figure 39 rise/fall times parameters table 47 output rise/fall times parame ters (operating conditions apply) parameter symbol limit values unit test conditions min. max. v ddp = 5v range rise/fall times t r , t f ?10 ns20 pf. 1) 2)3) 1) rise/fall time measurements are taken with 10% - 90% of pad supply. 2) not all parameters are 100% tested, but are verified by design/characterization and test correlation. 3) additional rise/fall time valid for c l = 20pf - 100pf @ 0.125 ns/pf. v ddp = 3.3v range rise/fall times t r , t f ?10 ns20 pf. 1) 2)4) 4) additional rise/fall time valid for c l = 20pf - 100pf @ 0.225 ns/pf. t r 10% 90% 10% 90% t f v ss v ddp
xc87xclm electrical parameters data sheet 124 v1.5, 2011-03 4.3.3 power-on reset and pll timing table 48 provides the characteristics of the po wer-on reset and pll timing in the xc87x. figure 40 power-on reset timing table 48 power-on reset and pll timi ng (operating co nditions apply) parameter symbol limit values unit test conditions min. typ. max. on-chip oscillator start-up time t oscst cc ? ? 500 ns 1) 1) not all parameters are 100% tested, but are verified by design/characterization and test correlation. pll lock-in in time t lock cc ? ? 200 s 1) pll accumulated jitter d p ??1.8ns 1)2) 2) pll lock at 144 mhz using a 4 mhz external oscillator. the pll divider settings are k = 2, n = 72 and p = 1. vddp pads vddc v pad osc t os cs t pll pll unlock pll lock t lock 1) pad state undefined 2)pull/input 3)as programmed i )unt il e v r is st able i i )unt il p ll is locked iii) reset is released and start of program
xc87xclm electrical parameters data sheet 125 v1.5, 2011-03 4.3.4 on-chip oscillator characteristics table 49 provides the characteristics of th e on-chip oscillator in the xc87x. table 49 on-chip oscillator characteri stics (operating conditions apply) parameter symbol limit values unit test conditions min. typ. max. nominal frequency f nom cc 3.88 4 4.12 mhz under nominal conditions 1) after ifx-backend trimming 1) nominal condition: v ddc =2.5v, t a =+25 c. long term frequency deviation ? f lt cc -5 ? 5 % with respect to f nom , over lifetime and temperature (-40 c to 105 c), for one given device after trimming short term frequency deviation ? f st cc -1.0 ? 1.0 % within one lin message (<10 ms .... 100 ms)
xc87xclm electrical parameters data sheet 126 v1.5, 2011-03 4.3.5 external data memory characteristics table 50 shows the timing of the exte rnal data memory read cycle. figure 41 external data memory read cycle table 50 external data memory read timing 1) (operating conditions apply) 1) external bus interface is not available in xc874. parameter symbol limit values unit test conditions min. max. rd pulse width t 1 cc 2* f cclk -17 - ns 2) 2) not all parameters are 100% tested, but are verified by design/characterization and test correlation. address valid to rd t 2 cc f cclk -12 - ns 2) rd to valid data in t 3 sr - 1.5* f cclk -27 ns 2) address to valid data in t 4 sr - 3* f cclk -7 ns 2) data hold after rd t 5 sr 0.5* f cclk -17 - ns 2) data address rd addresses d[ 7: 0] valid t 1 t 3 t 2 t 4 t 5
xc87xclm electrical parameters data sheet 127 v1.5, 2011-03 table 51 shows the timing of the exte rnal data memory write cycle. figure 42 external data memory write cycle table 51 external data memory write timing 1) (operating co nditions apply) 1) external bus interface is not available in xc874. parameter symbol limit values unit test conditions min. max. wr pulse width t 1 cc f cclk -10 - ns 2) 2) not all parameters are 100% tested, but are verified by design/characterization and test correlation. address valid to wr t 2 cc 2* f cclk -7 - ns 2) data valid to wr transition t 3 sr f cclk -5 - ns 2) data setup before wr t 4 sr 9* f cclk -13 - ns 2) data hold after wr t 5 sr 6* f cclk -3 - ns 2) data address wr addresses d[7:0] valid t 1 t 2 t 3 t 4 t 5
xc87xclm electrical parameters data sheet 128 v1.5, 2011-03 4.3.6 external clock drive xtal1 table 52 shows the parameters that define the external clock supply for xc87x. these timing parameters are based on the direct xta l1 drive of clock input signals. they are not applicable if an exte rnal crystal or ceramic resonator is considered. figure 43 external clock drive xtal1 table 52 external clock drive character istics (operating conditions apply) parameter symbol limit va lues unit test conditions min. max. oscillator period t osc sr 50 500 ns 1)2) 1) the clock input signals with 45-55% duty cycle are used. 2) not all parameters are 100% tested, but are verified by design/characterization and test correlation. high time t 1 sr 15 - ns 2)3) 3) the clock input signal must reach the defined levels v ilx and v ihx . low time t 2 sr 15 - ns 2)3) rise time t 3 sr - 10 ns 2)3) fall time t 4 sr - 10 ns 2)3) t 1 t 2 t 3 t 4 t osc 0.5 v ddc v ihx v ilx
xc87xclm electrical parameters data sheet 129 v1.5, 2011-03 4.3.7 jtag timing table 53 provides the characteristics of the jtag timing in the xc87x. figure 44 tck clock timing table 53 tck clock timing (operating conditio ns apply; cl = 50 pf) parameter symbol limits unit test conditions min max tck clock period t tck sr 50 - ns 1) 1) not all parameters are 100% tested, but are verified by design/characterization and test correlation. tck high time t 1 sr 20 - ns 1) tck low time t 2 sr 20 - ns 1) tck clock rise time t 3 sr - 4 ns 1) tck clock fall time t 4 sr - 4 ns 1) table 54 jtag timing (operating conditions apply; cl = 50 pf) parameter symbol limits unit test conditions min max tms setup to tck t 1 sr 8 - ns 1) tms hold to tck t 2 sr 0 - ns 1) tdi setup to tck t 1 sr 8 - ns 1) tdi hold to tck t 2 sr 4 - ns 1) tdo valid output from tck t 3 cc - 24 ns 5v device 1) - 31 ns 3.3v device 1) tck t 4 0.9 v ddp t 3 t 1 0.1 v ddp t 2 t tck 0.5 v ddp
xc87xclm electrical parameters data sheet 130 v1.5, 2011-03 figure 45 jtag timing tdo high impedan ce to valid output from tck t 4 cc - 18 ns 5v device 1) - 21 ns 3.3v device 1) tdo valid output to high impedance from tck t 5 cc - 21 ns 5v device 1) - 20 ns 3.3v device 1) 1) not all parameters are 100% tested, but are verified by design/characterization and test correlation. table 54 jtag timing (operating conditions apply; cl = 50 pf) (cont?d) parameter symbol limits unit test conditions min max tms tdi tck tdo t 1 t 2 t 1 t 2 t 4 t 3 t 5
xc87xclm electrical parameters data sheet 131 v1.5, 2011-03 4.3.8 ssc master mode timing table 55 provides the characteristics of the ssc timing in the xc87x. figure 46 ssc master mode timing table 55 ssc master mode timing (ope rating conditions apply; cl = 50 pf) parameter symbol limit values unit test conditions min. max. sclk clock period t 0 cc 2*t ssc ?ns 1)2) 1) t sscmin =t cpu =1/f cpu . when f cpu = 24 mhz, t 0 = 83.3ns. t cpu is the cpu clock period. 2) 1not all parameters are 100% tested, but are veri fied by design/characterization and test correlation. mtsr delay from sclk t 1 cc 0 5 ns 2) mrst setup to sclk t 2 sr 13 ? ns 2) mrst hold from sclk t 3 sr 0 ? ns 2) ssc_tmg1 sclk 1) mtsr 1) t 1 t 1 mrst 1) t 3 data valid t 2 t 1 1) this timing is based on the following setup: con.ph = con.po = 0. t 0
xc87xclm package and quality declaration data sheet 133 v1.5, 2011-03 5 package and quality declaration chapter 5 provides the information of the xc 87x package and reliability section. 5.1 package parameters table 56 provides the thermal ch aracteristics of the packa ge used in xc878 and xc874. table 56 thermal characteristics of the packages parameter symbol limit values unit notes min. max. pg-lqfp-64-4 (xc878) thermal resistance junction case 1) 1) the thermal resistances between the case and the ambient ( r tca ) , the lead and the ambient ( r tla ) are to be combined with the thermal resistances between the junction and the case ( r tjc ), the junction and the lead ( r tjl ) given above, in order to calculate the total thermal resistance between the junction and the ambient ( r tja ). the thermal resistances between the case and the ambient ( r tca ), the lead and the ambient ( r tla ) depend on the external system (pcb, case) characteristics, and are under user responsibility. the junction temperature can be calculated using the following equation: t j = t a + r tja p d , where the r tja is the total thermal resistance between the junction and the ambient. this total junction ambient resistance r tja can be obtained from the upper four partial thermal resistances, by a) simply adding only the two thermal resistances (junction lead and lead ambient), or b) by taking all four resistances into account, depending on the precision needed. r tjc cc - 13.8 k/w - thermal resistance junction lead 1) r tjl cc - 34.6 k/w - pg-vqfn-48-22 (xc874) thermal resistance junction case 1) r tjc cc - 16.6 k/w - thermal resistance junction lead 1) r tjl cc - 30.7 k/w -
xc87xclm package and quality declaration data sheet 134 v1.5, 2011-03 5.2 package outline figure 47 shows the package ou tlines of the xc878. figure 47 pg-lqfp-64 -4 package outline
xc87xclm package and quality declaration data sheet 135 v1.5, 2011-03 figure 48 shows the package ou tlines of the xc874. figure 48 pg-vqfn-48- 22 package outline
xc87xclm package and quality declaration data sheet 136 v1.5, 2011-03 5.3 quality declaration table 57 shows the characteristics of t he quality parameters in the xc87x. table 57 quality parameters parameter symbol limit values unit notes min. max. operation lifetime when the device is used at the two stated t j 1) 1) this lifetime refers only to the time when device is powered-on. t op1 - 15000 hours t j =110 c - 2000 hours t j =-40 c operation lifetime when the device is used at the five stated t j 1) t op2 - 120 hours t j =140 c - 960 hours t j =135 c - 7800 hours t j =91 c - 2400 hours t j =38 c - 720 hours t j =-25 c esd susceptibility according to human body model (hbm) v hbm - 2000 v conforming to eia/jesd22- a114-b esd susceptibility according to charged device model (cdm) pins v cdm - 750 v conforming to jesd22-c101-c
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